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參數(shù)資料
| 型號： | 4565B2 |
| 廠商： | LSI CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | ATM/SONET/SDH SUPPORT CIRCUIT, PBGA909 |
| 封裝： | PLASTIC, BGA-909 |
| 文件頁數(shù)： | 21/61頁 |
| 文件大?。?/td> | 1691K |
| 代理商： | 4565B2 |
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4565B Ultramapper Full Transport Retiming Device
Hardware Design Guide, Revision 2
622/155 Mbits/s SONET/SDH x DS3/E3/DS2/DS1/E1
December 17, 2003
28
Agere Systems Inc.
Table 2-20. Clock Generator
Pin
Symbol
Type
Name/Description
AF27
CLKIN_PLL
I pd
Transmit Line Clock Generator Reference Input. The clock generator is used
used to devise the transmit line clocks for DS1/E1 synchronized to CLKIN_PLL.
The derived clock is used in the DS1/E1 transmit framer sections.
If used for retiming applications, this clock should be tied to CHIRX/TXGCLK.
AF26
CG_PLLCLKOUT
O
Framer PLL Test Mode Output. Framer PLL clock (1.544 MHz, 2.048 MHz)
selected by the device register.
AK31, AG30,
AJ31
MODE[2:0]_PLL
I pd
Framer PLL Input Clock Mode Select Bits. The settings of these mode select
pins must correspond to the frequency of CLKIN_PLL as shown below.
MODE[2:0]_PLL
CLKIN_PLL
MODE[2:0]_PLL
CLKIN_PLL
000
Reserved
100
16.384 MHz
001
51.840 MHz
101
8.192 MHz
010
26.624 MHz
110
4.096 MHz
011
19.440 MHz
111
2.048 MHz
Table 2-21. Microprocessor Interface
Pin
Symbol
Type
Name/Description
G4
MPCLK
I
Microprocessor Clock. This clock is required to properly sample address, data,
and control signals from the microprocessor in both asynchronous and synchro-
nous modes of operation.
D2
MPMODE
I
Microprocessor Mode. If the microprocessor interface is synchronous, MPMODE
should be set to 1. If the microprocessor interface is asynchronous, MPMODE
should be set to 0.
G7
CSN
I pu Chip Select. Active-low high-order address signal. Chip select must be set low at
the beginning of any read or write access and returned high at the end of the cycle.
F3
ADSN
I
Address Strobe. Active-low address strobe that indicates the beginning of a read
or write access. It is a one MPCLK cycle-wide pulse for synchronous mode. In
asynchronous mode, it is active for the entire read/write cycle. Address bus sig-
nals, ADDR[20:0], are available to the 4565B Ultramapper Full Transport Retiming
Device when ADSN is low. The address bus should remain valid for the duration of
ADSN.
J6
RWN
I
Read/Write. RWN is set high during a read cycle, or set low during a write cycle.
J5
DSN
I
Data Strobe. For a read cycle, the contents of the internal register will be output
on DATA [15:0]. For a write cycle, the DATA [15:0] will be clocked into the internal
register. To initiate the start of the read/write operation, DSN must be low during
the entire read/write cycle. This signal should only be used for asynchronous
mode.
N5, P8, M4, L3,
J1, N6, M5, L8,
K4, M6, H2, L5,
L6, G2, F1, K5,
J4, J8, G3, H4,
K6
ADDR[20:0]
I
Address [20:0]. ADDR[20] is the MSB and ADDR[0] is the LSB for addressing all
the internal registers during microprocessor access cycles. All addresses are
21-bit word addresses; therefore, in a typical application, ADDR[0] of the 4565B
device would be connected to address bit 1 of a byte-addressable system address
bus.
Note: The 4565B Ultramapper Full Transport Retiming Device is little endian, i.e.,
the least significant byte is stored in the lowest address and the most signif-
icant byte is stored in the highest address. Care must be exercised in con-
nection with microprocessors that use big endian byte ordering.
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