參數(shù)資料
型號： 5962-8967401QX
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
封裝： CERAMIC, DIP-40
文件頁數(shù)： 13/34頁
文件大?。?/td> 860K
代理商： 5962-8967401QX
MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
20
______________________________________________________________________________________
CONTROL
BITS
DATA
BITS
DATA
C3
C2
C1
C0
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
FUNCTION
INPUT
REGISTERS
(A–D)
DIN
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACA
input
register
from
shift
register;
DACA
output
register
is
unchanged;
DACA
output
is
unchanged.*
DIN
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACA
output
register
from
shift
register;
input
register
is
unchanged;
DACA
output
is
updated.*
DIN
0
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACA
input
register
and
output
register
from
shift
register;
DACA
output
is
updated
.*
DIN
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACB
input
register
from
shift
register;
DACB
output
register
is
unchanged;
DACB
output
is
unchanged.*
DIN
0
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACB
output
register
from
shift
register;
input
register
is
unchanged.
DACB
output
is
updated.*
DIN
0
1
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACB
input
register
and
output
register
from
shift
register;
DACB
output
is
updated
.*
DIN
0
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACC
input
register
from
shift
register;
DACC
output
register
is
unchanged;
DACC
output
is
unchanged.*
DIN
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACC
output
register
from
shift
register;
input
register
is
unchanged;
DACC
output
is
updated.*
DIN
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACC
input
register
and
output
register
from
shift
register;
DACC
output
is
updated
.*
DIN
1
0
1
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACD
input
register
from
shift
register;
DACD
output
register
is
unchanged;
DACD
output
is
unchanged.*
DIN
1
0
1
0
D11
D10
D9
D8
D7
D6
D5
D4
D3/0
D2/0
D1/0
D0/0
Load
DACD
output
register
from
shift
register;
input
register
is
unchanged;
DACD
output
is
updated.*
Table
2a.
DAC
Programming
Commands
相關(guān)PDF資料
PDF描述
5962-8967402QX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967402XX 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
5962-8967601QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967601QX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40
5962-8967601XX 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44
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