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| 型號： | 5962-8967401QX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 19/34頁 |
| 文件大?。?/td> | 860K |
| 代理商： | 5962-8967401QX |
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MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
26
______________________________________________________________________________________
Settling-Time-Mode Write Example:
To configure DACA and DACD into FAST mode and
DACB and DACC into SLOW mode, use the command
in Table 12.
To read back the settling-time-mode bits, use the com-
mand in Table 13.
CPOL and CPHA Control Bits
The
CPOL
and
CPHA
control
bits
of
the
MAX5580–MAX5585 are defined the same as the CPOL
and CPHA bits in the SPI standard. Set the DAC’s
CPOL and CPHA bits to CPOL = 0 and CPHA = 0 or
CPOL = 1 and CPHA = 1 for MICROWIRE and SPI
applications requiring the clocking of data in on the ris-
ing edge of SCLK. Set the DAC’s CPOL and CPHA bits
to CPOL = 0 and CPHA = 1 or CPOL = 1 and CPHA =
0 for DSP and SPI applications, requiring the clocking
of data in on the falling edge of SCLK (refer to the
Programmer’s Handbook and see Table 14 for details).
At power-up, if DSP = DVDD, the default value of CPHA
is zero and if DSP = DGND, the default value of CPHA
is one. The default value of CPOL is zero at power-up.
To write to the CPOL and CPHA bits, use the command
in Table 15.
To read back the device’s CPOL and CPHA bits, use
the command in Table 16.
Table 12. Settling-Time-Mode Write Example
DATA
CONTROL BITS
DATA BITS
DIN
11
10
11
0X
X
10
01
X = Don’t care.
Table 13. Settling-Time-Mode Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
11
011
11
X
DOUTRB
X
XX
XXX
X
SPDD SPDC SPDBSPDA
Table 16. CPOL and CPHA Read Command
DATA
CONTROL BITS
DATA BITS
DIN
1
0
1
X
DOUTRB
X
XX
X
XX
X
CPOLCPHA
Table 14. CPOL and CPHA Bits
CPOL
CPHA
DESCRIPTION
00
Default values at power-up when DSP is connected to DVDD. Data is clocked in on the rising edge
of SCLK.
01
Default values at power-up when DSP is connected to DGND. Data is clocked in on the falling edge
of SCLK.
1
0
Data is clocked in on the falling edge of SCLK.
1
Data is clocked in on the rising edge of SCLK.
Table 15. CPOL and CPHA Write Command
DATA
CONTROL BITS
DATA BITS
DIN
11
1
00
00X
X
CPOLCPHA
X = Don’t care.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 5962-8967402QX | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 5962-8967402XX | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44 |
| 5962-8967601QX | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 5962-8967601QX | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 5962-8967601XX | 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CQCC44 |
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