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參數(shù)資料
| 型號： | 5962-8967401QX |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數(shù)： | 31/34頁 |
| 文件大?。?/td> | 860K |
| 代理商： | 5962-8967401QX |
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MAX5580–MAX5585
Buffered, Fast-Settling, Quad,
12-/10-/8-Bit, Voltage-Output DACs
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS—DSP Mode Disabled (3V, 3.3V, 5V Logic) (Figure 1)
(DVDD = 2.7V to 5.25V, AGND = DGND = 0, TA = TMIN to TMAX, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Frequency
fSCLK
2.7V < DVDD < 5.25V
20
MHz
SCLK Pulse-Width High
tCH
(Note 7)
20
ns
SCLK Pulse-Width Low
tCL
(Note 7)
20
ns
CS Fall to SCLK Rise Setup Time
tCSS
10
ns
SCLK Rise to CS Rise Hold Time
tCSH
5ns
SCLK Rise to CS Fall Setup Time
tCS0
10
ns
DIN to SCLK Rise Setup Time
tDS
12
ns
DIN to SCLK Rise Hold Time
tDH
5ns
SCLK Rise to DOUTDC1 Valid
Propagation Delay
tDO1
CL = 20pF, UPIO_ = DOUTDC1 mode
30
ns
SCLK Fall to DOUT_ Valid
Propagation Delay
tDO2
CL = 20pF, UPIO_ = DOUTDC0 or DOUTRB
mode
30
ns
CS Rise to SCLK Rise Hold Time
tCS1
MICROWIRE and SPI modes 0 and 3
10
ns
CS Pulse-Width High
tCSW
45
ns
UPIO_ TIMING CHARACTERISTICS
DOUT Tri-State Time when Exiting
DOUTDC0, DOUTDC1, and UPIO
Modes
tDOZ
CL = 20pF, from end of write cycle to UPIO_
in high impedance
100
ns
DOUTRB Tri-State Time from CS
Rise
tDRBZ
CL = 20pF, from rising edge of CS to UPIO_
in high impedance
20
ns
DOUTRB Tri-State Enable Time
from 8th SCLK Rise
tZEN
CL = 20pF, from 8th rising edge of SCLK to
UPIO_ driven out of tri-state
0ns
LDAC Pulse-Width Low
tLDL
Figure 5
20
ns
LDAC Effective Delay
tLDS
Figure 6
100
ns
CLR, MID, SET Pulse-Width Low
tCMS
Figure 5
20
ns
GPO Output Settling Time
tGP
Figure 6
100
ns
GPO Output High-Impedance
Time
tGPZ
100
ns
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| 5962-8967402QX | 1-CH 14-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL/PARALLEL ACCESS, CDIP40 |
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