參數(shù)資料
型號： 70T3399S133BCGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： SRAM
英文描述： 128K X 18 DUAL-PORT SRAM, 15 ns, PBGA256
封裝： 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
文件頁數(shù)： 4/28頁
文件大?。?/td> 327K
代理商： 70T3399S133BCGI8
6.42
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing) (2,3) (VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when
FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when
FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (
OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 6 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5.
200Mhz is not available in the BF-208 and DD-144 packages.
6. Guaranteed by design (not production tested).
70T3339/19/99
S200
Com'l Only
(5)
70T3339/19/99
S166
Com'l
& Ind(4)
70T3339/19/99
S133
Com'l
& Ind
Symbol
Parameter
Min.Max.Min.Max.Min.
Max.
Unit
tCYC1
Clock Cycle Time (Flow-Through)(1)
15
____
20
____
25
____
ns
tCYC2
Clock Cycle Time (Pipelined)
(1)
5
____
6
____
7.5
____
ns
tCH1
Clock High Time (Flow-Through)(1)
6
____
8
____
10
____
ns
tCL1
Clock Low Time (Flow-Through)(1)
6
____
8
____
10
____
ns
tCH2
Clock High Time (Pipelined)
(2)
2
____
2.4
____
3
____
ns
tCL2
Clock Low Time (Pipelined)(1)
2
____
2.4
____
3
____
ns
tSA
Address Setup Time
1.5
____
1.7
____
1.8
____
ns
tHA
Address Hold Time
0.5
____
0.5
____
0.5
____
ns
tSC
Chip Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHC
Chip Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSB
Byte Enable Setup Time
1.5
____
1.7
____
1.8
____
ns
tHB
Byte Enable Hold Time
0.5
____
0.5
____
0.5
____
ns
tSW
R/W Setup Time
1.5
____
1.7
____
1.8
____
ns
tHW
R/W Hold Time
0.5
____
0.5
____
0.5
____
ns
tSD
Input Data Setup Time
1.5
____
1.7
____
1.8
____
ns
tHD
Input Data Hold Time
0.5
____
0.5
____
0.5
____
ns
tSAD
ADS Setup Time
1.5
____
1.7
____
1.8
____
ns
tHAD
ADS Hold Time
0.5
____
0.5
____
0.5
____
ns
tSCN
CNTEN Setup Time
1.5
____
1.7
____
1.8
____
ns
tHCN
CNTEN Hold Time
0.5
____
0.5
____
0.5
____
ns
tSRPT
REPEAT Setup Time
1.5
____
1.7
____
1.8
____
ns
tHRPT
REPEAT Hold Time
0.5
____
0.5
____
0.5
____
ns
tOE
Output Enable to Data Valid
____
4.4
____
4.4
____
4.6
ns
tOLZ(6)
Output Enable to Output Low-Z
1
____
1
____
1
____
ns
tOHZ
(6)
Output Enable to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCD1
Clock to Data Valid (Flow-Through)(1)
____
10
____
12
____
15
ns
tCD2
Clock to Data Valid (Pipelined)
(1)
____
3.4
____
3.6
____
4.2
ns
tDC
Data Output Hold After Clock High
1
____
1
____
1
____
ns
tCKHZ
(6)
Clock High to Output High-Z
1
3.4
1
3.6
1
4.2
ns
tCKLZ
(6)
Clock High to Output Low-Z
1
____
1
____
1
____
ns
tINS
Interrupt Flag Set Time
____
7
____
7
____
7ns
tINR
Interrupt Flag Reset Time
____
7
____
7
____
7ns
tCOLS
Collision Flag Set Time
____
3.4
____
3.6
____
4.2
ns
tCOLR
Collision Flag Reset Time
____
3.4
____
3.6
____
4.2
ns
tZZSC
Sleep Mode Set Cycles
2
____
2
____
2
____
cycles
tZZRC
Sleep Mode Recovery Cycles
3
____
3
____
3
____
cycles
Port-to-Port Delay
tCO
Clock-to-Clock Offset
4
____
5
____
6
____
ns
tOFS
Clock-to-Clock Offset for Collision Detection
Please refer to Collision Detection Timing Table on Page 21
5652 tbl 11
相關(guān)PDF資料
PDF描述
70TPS12 75 A, 1200 V, SCR, TO-274AA
70TPS16 75 A, 1600 V, SCR, TO-274AA
70TPS12PBF 75 A, 1200 V, SCR, TO-274AA
70TPS16PBF 75 A, 1600 V, SCR, TO-274AA
70V657S12BFG8 32K X 36 DUAL-PORT SRAM, 12 ns, PBGA208
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
70T3399S133BCI 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Rail/Tube
70T3399S133BCI8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 256-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 256BGA - Tape and Reel
70T3399S133BF 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube
70T3399S133BF8 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Tape and Reel
70T3399S133BFI 制造商:Integrated Device Technology Inc 功能描述:SRAM Chip Sync Dual 2.5V 2M-Bit 128K x 18 15ns/4.2ns 208-Pin CABGA Tray 制造商:Integrated Device Technology Inc 功能描述:SRAM SYNC DUAL 2.5V 2.25MBIT 128KX18 15NS/4.2NS 208FPBGA - Rail/Tube
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*