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參數(shù)資料
| 型號(hào)： | 70V18L15PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 16/17頁(yè) |
| 文件大小： | 157K |
| 代理商： | 70V18L15PF8 |
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IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
8
4854 drw 08
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
R/
W
tAW
tEW
(3)
(2)
(6)
CE or SEM(9,10)
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
NOTES:
1. R/
W or CE = VIH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a
CE = VIL and a R/W = VIL for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If
OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus
for the required tDW. If
OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access RAM,
CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Truth Table I - Chip Enable .
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
CE or SEM
(6)
(4)
(3)
4854 drw 07
(7)
(9)
(7)
tLZ
,
tHZ
(7)
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