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參數(shù)資料
| 型號： | 70V18L15PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 70V18L15PF8 |
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
12
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
70V18L15
Com'l Only
70V18L20
Com'l
& Ind
Symbol
Parameter
Min.Max.Min.Max.
Unit
INTERRUPT TIMING
tAS
Address Set-up Time
0
____
0
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tINS
Interrupt Set Time
____
15
____
20
ns
tINR
Interrupt Reset Time
____
15
____
20
ns
4854 tbl 15
Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1,3)
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing (M/S = VIH)(1)
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the
BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
3. Refer to Truth Table I - Chip Enable.
4854 drw 13
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
CE"B"
BUSY"B"
tAPS
tBAC
tBDC
(2)
4854 drw 14
ADDR"A"
ADDRESS "N"
ADDR"B"
BUSY"B"
tAPS
tBAA
tBDA
(2)
MATCHING ADDRESS "N"
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