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參數(shù)資料
| 型號： | 70V18L15PF8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | SRAM |
| 英文描述： | 64K X 9 DUAL-PORT SRAM, 15 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 6/17頁 |
| 文件大?。?/td> | 157K |
| 代理商： | 70V18L15PF8 |
IDT70V18L
High-Speed 3.3V 64K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
14
Functional Description
The IDT70V18 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V18 has an automatic power down
feature controlled by
CE. The CE0 and CE1 control the on-chip power
down circuitry that permits the respective port to go into a standby
mode when not selected (
CE = VIH). When a port is enabled, access
to the entire memory array is permitted.
Interrupts
If the user chooses the interrupt function, a memory location (mail
box or message center) is assigned to each port. The left port interrupt
flag (
INTL) is asserted when the right port writes to memory location
FFFE (HEX), where a write is defined as
CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
address location FFFE when
CEL = OEL = VIL, R/W is a "don't care".
Likewise, the right port interrupt flag (
INTR) is asserted when the left
port writes to memory location FFFF (HEX) and to clear the interrupt
flag (
INTR), the right port must read the memory location FFFF. The
message (9 bits) at FFFE or FFFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations FFFE and FFFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table IV for the
interrupt operation.
Truth Table V —
Address BUSY Arbitration(4)
NOTES:
1.
Pins
BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V18 are push-
pull, not open drain outputs. On slaves the
BUSY input internally inhibits writes.
2.
"L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either
BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3.
Writes to the left port are internally ignored when
BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Truth Table I - Chip Enable.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2,3)
NOTES:
1.
This table denotes a sequence of events for only one of the eight semaphores on the IDT70V18.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
3.
CE = VIH, SEM = VIL to access the semaphores. Refer to Truth Table III - Semaphore Read/Write Control.
Inputs
Outputs
Function
CEL
CER
AOL-A15L
AOR-A15R
BUSYL(1)
BUSYR(1)
X
NO MATCH
H
Normal
H
X
MATCH
H
Normal
X
H
MATCH
H
Normal
LL
MATCH
(2)
Write Inhibit(3)
4854 tbl 17
Functions
D0 - D8 Left
D0 - D8 Right
Status
No Action
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Right Port Writes "0" to Semaphore
0
1
No change. Right side has no write access to semaphore
Left Port Writes "1" to Semaphore
1
0
Right port obtains semaphore token
Left Port Writes "0" to Semaphore
1
0
No change. Left port has no write access to semaphore
Right Port Writes "1" to Semaphore
0
1
Left port obtains semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
Right Port Writes "0" to Semaphore
1
0
Right port has semaphore token
Right Port Writes "1" to Semaphore
1
Semaphore free
Left Port Writes "0" to Semaphore
0
1
Left port has semaphore token
Left Port Writes "1" to Semaphore
1
Semaphore free
4854 tbl 18
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