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參數(shù)資料
| 型號： | 73K322L |
| 廠商： | TDK Corporation |
| 英文描述： | CCITT V.23, V.22, V.21 Single-Chip Modem(CCITT V.23, V.22, V.21單片Modem) |
| 中文描述： | 國際電話電報諮詢委員會.23，.22，.21單芯片調(diào)制解調(diào)器（國際電話電報諮詢委員會.23，.22，.21單片調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 2/30頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 73K322L |
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73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
2
DESCRIPTION
(continued)
asynchronous communications. The 73K322L is
designed to appear to the systems designer as a
microprocessor peripheral, and will easily interface
with popular one-chip microprocessors (80C51
typical) for control of modem functions through its 8-
bit multiplexed address/data bus or via an optional
serial control bus. An ALE control line simplifies
address
demultiplexing.
occurs through a separate serial port only.
Data
communications
The 73K322L is ideal for use in either free standing
or integral system modem products where multi-
standard data communications over the 2-wire
switched telephone network is desired. Its high
functionality, low power consumption and efficient
packaging
simplify
design
increase system reliability. A complete modem
requires only the addition of the phone line interface,
a control microprocessor, and RS-232 level
converter for a typical system. The 73K322L is part
of TDK Semiconductor Corporation K-Series family
of pin and function compatible single-chip modem
products. These devices allow systems to be
configured for higher speeds and Bell or CCITT
operation with only a single component change.
OPERATION
ASYNCHRONOUS MODE
Data transmission for the DPSK mode requires that
data ultimately be transmitted in a synchronous
fashion. The 73K322L includes ASYNC/SYNC and
SYNC/ASYNC converters which delete or insert stop
bits in order to transmit data at a regular rate. In
Asynchronous mode the serial data comes from the
TXD pin into the ASYNC/SYNC converter. The
ASYNC/SYNC converter accepts the data provided
on the TXD pin which normally must be 1200 or 600
bit/s +1.0%, -2.5%. The rate converter will then
insert or delete stop bits in order to output a signal
which is 1200 or 600 bit/s ± 0.01% (± 0.01% is the
crystal tolerance).
requirements
and
The SYNC/ASYNC converter also has an extended
overspeed mode which allows selection of an output
overspeed range of either +1% or +2.3%. In the
extended overspeed mode, stop bits are output at
7/8 the normal width.
The serial data stream from the transmit buffer or the
rate converter is passed through the data scrambler
and onto the analog modulator. The data scrambler
can be bypassed under processor control when
unscrambled data must be transmitted. If serial input
data contains a break signal through one character
(including start and stop bits) the break will be
extended to at least 2 times N + 3 bits long (where N
is the number of transmitted bits/character).
Serial data from the demodulator is passed first
through the data descrambler and then through the
SYNC/ASYNC
converter.
converter will reinsert any deleted stop bits and output
data at an intra-character rate (bit-to-bit timing) of no
greater than 1219 bit/s. An incoming break signal
(low through two characters) will be passed through
without incorrectly inserting a stop bit.
SYNCHRONOUS MODE
The CCITT V.22 standard defines synchronous
operation at 600 and 1200 bit/s. Operation is similar
to that of the Asynchronous mode except that data
must be synchronized to a provided clock and no
variation in data transfer rate is allowable. Serial
input data appearing at TXD must be valid on the
rising edge of TXCLK.
The
ASYNC/ASYNC
TXCLK is an internally derived signal in Internal
mode and is connected internally to the RXCLK pin
in Slave mode. Receive data at the RXD pin is
clocked out on the falling edge of RXCLK. The
ASYNCH/SYNCH converter is bypassed when
Synchronous mode is selected and data is
transmitted out at the same rate as it is input.
DPSK MODULATOR/DEMODULATOR
In DPSK mode the 73K322L modulates a serial bit
stream into di-bit pairs that are represented by four
possible phase shifts as prescribed by the V.22
standards. The base-band signal is then filtered to
reduce intersymbol interference on the bandlimited
2-wire telephone line. Transmission occurs using
either a 1200 Hz (Originate mode) or 2400 Hz carrier
(Answer mode). Demodulation is the reverse of the
modulation process, with the incoming analog signal
eventually decoded into di-bits and converted back
to a serial bit stream. The demodulator also recovers
the clock which was encoded into the analog signal
during modulation. Demodulation occurs using either
a 1200 Hz carrier (Answer mode or ALB Originate
mode) or a 2400 Hz carrier (Originate mode or ALB
Answer mode). The 73K322L uses a phase locked
loop coherent demodulation technique for optimum
receiver performance.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 73M223 | 1200 Baud FSK Modem |
| 73M223-CL | 1200 Baud FSK Modem |
| 73M223-CP | 1200 Baud FSK Modem |
| 73M2901CL | V.22 BIS SINGLE CHIP MODEM |
| 73M2901CLIGT | V.22 BIS SINGLE CHIP MODEM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K322L-IH | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K322L-IP | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K324BL | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single-Chip Modem w/ Integrated Hybrid |
| 73K324BL-IGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
| 73K324BL-IH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
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