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參數(shù)資料
| 型號： | 73K322L |
| 廠商： | TDK Corporation |
| 英文描述： | CCITT V.23, V.22, V.21 Single-Chip Modem(CCITT V.23, V.22, V.21單片Modem) |
| 中文描述： | 國際電話電報諮詢委員會.23，.22，.21單芯片調(diào)制解調(diào)器（國際電話電報諮詢委員會.23，.22，.21單片調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 5/30頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 73K322L |
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73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
5
PARALLEL MICROPROCESSOR CONTROL INTERFACE
(continued)
NAME
PLCC/DIP
PIN NUMBER
TYPE
DESCRIPTION
WR
13
I
Write. A low on this informs the 73K322L that data is available on
AD0-AD7 for writing into an internal register. Data is latched on the
rising edge of
WR
. No data is written unless both
WR
and the latched
CS
are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE
AD0-AD2
4-6
I
Register Address Selection. These lines carry register addresses and
should be valid during any read or write operation.
AD7
11
I/O
Serial Control Data Input/Output. Data for a read/write operation is
clocked in or out on the falling edge of the EXCLK pin. The direction
of data flow is controlled by the
RD
pin.
RD
low outputs data.
RD
high
inputs data.
RD
14
I
Read. A low on this input informs the 73K322L that data or status
information is being read by the processor. The falling edge of the
RD
signal will initiate a read from the addressed register. The
RD
signal
must continue for eight falling edges of EXCLK in order to read all
eight bits of the referenced register. Read data is provided LSB first.
Data will not be output unless the
RD
signal is active.
WR
13
I
Write. A low on this input informs the 73K322L that data or status
information has been shifted in through the DATA pin and is available
for writing to an internal register. The normal procedure for a write is
to shift in data LSB first on the DATA pin for eight consecutive falling
edges of EXCLK and then to pulse
WR
low. Data is written on the
rising edge of
WR
.
Note:
The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes
the data input and AD0, AD1 and AD2 become the address only. See Serial Control timing diagrams on
pages 22 and 23.
DTE USER INTERFACE
NAME
PLCC/DIP
PIN NUMBER
TYPE
DESCRIPTION
EXCLK
19
I
External Clock. This signal is used only in synchronous DPSK
transmission when the external timing option has been selected. In
the External Timing mode the rising edge of EXCLK is used to strobe
synchronous DPSK transmit data available on the TXD pin. Also used
for serial control interface.
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| 73M223-CL | 1200 Baud FSK Modem |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K322L-IH | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K322L-IP | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K324BL | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single-Chip Modem w/ Integrated Hybrid |
| 73K324BL-IGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
| 73K324BL-IH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
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