參數(shù)資料
型號(hào): 73K322L
廠商: TDK Corporation
英文描述: CCITT V.23, V.22, V.21 Single-Chip Modem(CCITT V.23, V.22, V.21單片Modem)
中文描述: 國(guó)際電話電報(bào)諮詢委員會(huì).23,.22,.21單芯片調(diào)制解調(diào)器(國(guó)際電話電報(bào)諮詢委員會(huì).23,.22,.21單片調(diào)制解調(diào)器)
文件頁(yè)數(shù): 21/30頁(yè)
文件大?。?/td> 316K
代理商: 73K322L
73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
21
DYNAMIC CHARACTERISTICS AND TIMING PARALLEL CONTROL INTERFACE
PARAMETER
Guard Tone Generator
CONDITION
MIN
NOM
MAX
UNIT
Tone Accuracy
550 or 1800 Hz
-20
+20
Hz
550 Hz
-4.0
-3.0
-2.0
dB
Tone Level
(Below DPSK Output)
1800 Hz
-7.0
-6.0
-5.0
dB
Harmonic Distortion
700 to 2900 Hz
550 Hz
-50
dB
Timing
(Refer to Timing Diagrams)
CS
CS
setup before ALE Low
15
ns
TAL
ADDR
Address setup before ALE low
CS
/Address hold after ALE Low
ALE Low to
RD
/
WR
Low
RD
/
WR
Control to ALE High
Data out from
RD
Low
25
ns
TLA
15
ns
TLC
30
ns
TCL
-5
ns
TRD
140
ns
TLL
ALE width
30
ns
TRDF
Data float after RD High
RD
width
WR
width
Data setup before
WR
High
90
ns
TRW
200
ns
TWW
140
ns
TDW
25
ns
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using
non-8031 compatible processors, care must be taken to prevent this from occurring when designing the
interface logic.
ALE
RD
WR
AD0-AD7
CS
ADDRESS
READ DATA
ADDRESS
WRITE DATA
TLL
TLC
TRW
TCL
TAL
TLA
TRD
TRDF
TLC
TWW
TDW
TWD
BUS TIMING DIAGRAM
(PARALLEL CONTROL MODE)
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73K322L-IP 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem
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