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參數(shù)資料
| 型號(hào)： | 73K322L |
| 廠商： | TDK Corporation |
| 英文描述： | CCITT V.23, V.22, V.21 Single-Chip Modem(CCITT V.23, V.22, V.21單片Modem) |
| 中文描述： | 國(guó)際電話電報(bào)諮詢委員會(huì).23，.22，.21單芯片調(diào)制解調(diào)器（國(guó)際電話電報(bào)諮詢委員會(huì).23，.22，.21單片調(diào)制解調(diào)器） |
| 文件頁數(shù)： | 6/30頁 |
| 文件大?。?/td> | 316K |
| 代理商： | 73K322L |
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73K322L
CCITT V.23, V.22, V.21
Single-Chip Modem
6
RS-232 INTERFACE
(continued)
NAME
PLCC/DIP
PIN NUMBER
TYPE
DESCRIPTION
RXCLK
23
O
Receive Clock. The falling edge of this clock output is coincident with
the transitions in the serial received DPSK data output. The rising
edge of RXCLK can be used to latch the valid output data. RXCLK
will be valid as long as a carrier is present. In V.23 or V.21 mode a
clock which is 16 x 1200 (or 16 x 75) or 16 x 300 Hz baud data rate is
output, respectively, for driving a UART.
RXD
22
O
Received Data Output. Serial receive data is available on this pin.
The data is always valid on the rising edge of RXCLK when in
Synchronous mode. RXD will output constant marks if no carrier is
detected.
TXCLK
18
O
Transmit Clock. This signal is used only in synchronous DPSK
transmission to latch serial input data on the TXD pin. Data must be
provided so that valid data is available on the rising edge of the
TXCLK. The transmit clock is derived from different sources
depending upon the Synchronization mode selection. In Internal
Mode the clock is 1200 Hz generated internally. In External Mode
TXCLK is phase locked to the EXCLK pin. In Slave Mode TXCLK is
phase locked to the RXCLK pin. TXCLK is always active. In V.23 or
V.21 mode the output is a 16 x 1200 (or 16 x 75) or 16 x 300 Hz baud
clock, respectively for driving a UART.
TXD
21
I
Transmit Data Input. Serial data for transmission is applied on this
pin. In Synchronous modes, the data must be valid on the rising
edge of the TXCLK clock. In Asynchronous modes (1200 or 300
baud) no clocking is necessary. DPSK must be 1200/600 bit/s +1%, -
2.5% or +2.3%, -2.5% in Extended Overspeed mode.
ANALOG INTERFACE AND OSCILLATOR
RXA
27
I
Received modulated analog signal input from the telephone line
interface.
TXA
16
O
Transmit analog output to the telephone line interface.
XTL1
XTL2
2
3
I
I
These pins are for the internal crystal oscillator requiring a 11.0592
MHz Parallel mode crystal and two load capacitors to Ground. XTL2
can also be driven from an external clock.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 73K322L-IH | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K322L-IP | 制造商:TDK 制造商全稱:TDK Electronics 功能描述:CCITT V.23, V.22, V.21 Single-Chip Modem |
| 73K324BL | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Single-Chip Modem w/ Integrated Hybrid |
| 73K324BL-IGT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
| 73K324BL-IH | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Modem w/Integrated Hybrid |
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