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參數(shù)資料
| 型號： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 18/54頁 |
| 文件大?。?/td> | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 18 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 17 Interrupt control
Fig. 18 Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
(INTEDGE : address 003A
16
, initial value : 00
16
)
INT
0
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Disable (returns
“
0
”
when read)
P0
0
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
Interrupt request register 1
(IREQ1 : address 003C
16
, initial value : 00
16
)
Serial I/O receive interrupt request bit
Serial I/O transmit interrupt request bit
INT
0
interrupt request bit
INT
1
interrupt request bit
Key-on wake up interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer X interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0
Interrupt control register 1
(ICON1 : address 003E
16
, initial value : 00
16
)
Serial I/O receive interrupt enable bit
Serial I/O transmit interrupt enable bit
INT
0
interrupt enable bit
INT
1
interrupt enable bit
Key-on wake up interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Timer X interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt request register 2
(IREQ2 : address 003D
16
, initial value : 00
16
)
Disable (returns
“
0
”
when read)
Disable (returns
“
0
”
when read)
Timer A interrupt request bit
Disable (returns
“
0
”
when read)
A-D conversion interrupt request bit
Timer 1 interrupt request bit
Disable (returns
“
0
”
when read)
0 : No interrupt request issued
1 : Interrupt request issued
b7 b0
Interrupt control register 2
(ICON2 : address 003F
16
, initial value : 00
16
)
Disable (returns
“
0
”
when read)
Disable (returns
“
0
”
when read)
Timer A interrupt enable bit
Disable (returns
“
0
”
when read)
A-D conversion interrupt enable bit
Timer 1 interrupt enable bit
Disable (returns
“
0
”
when read)
(Do not write
“
1
”
to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
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| D348D | Logic IC |
| 7545ARPDS-2 | HIGH VOLTAGE, LOW QUIESCENT CURRENT LDO, -40C to +125C, 3-SOT-89, T/R |
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| 754-4.47M | 制造商:OSCILENT 制造商全稱:Oscilent Corporation 功能描述:Ceramic Trap Double/Triple Peak |
| 754-4.6M | 制造商:OSCILENT 制造商全稱:Oscilent Corporation 功能描述:Ceramic Trap Double/Triple Peak |
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