參數(shù)資料
型號(hào)： 7544
英文描述： 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述： 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁(yè)數(shù)： 25/54頁(yè)
文件大小： 503K
代理商： 7544
Rev.1.02 2003.06.25 page 25 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 26 Block diagram of clock synchronous serial I/O
Fig. 27 Operation of clock synchronous serial I/O function
Serial I/O
G
Serial I/O
Serial I/O can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register (bit 6)
to
“
1
”
.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
1/4
1/4
F/F
P1
2
/S
CLK
Serial I/O status register
Serial I/O control register
P1
3
/S
RDY
P1
0
/R
X
D
P1
1
/T
X
D
X
IN
Receive buffer
register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control
circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C
16
BRG count source selection bit
Clock control
circuit
Falling-edge
detector
Transmit buffer register
Data bus
Address 0018
16
Shift clock
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 0019
16
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Data bus
Address 001A
16
Transmit shift register
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register (address 0018
16
)
Notes 1:
As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2:
If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3:
The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes
“
1
”
.
Receive enable signal
S
RDY
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