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參數(shù)資料
| 型號： | 7544 |
| 英文描述： | 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL. |
| 中文描述： | 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03 |
| 文件頁數(shù)： | 22/54頁 |
| 文件大小： | 503K |
| 代理商： | 7544 |
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Rev.1.02 2003.06.25 page 22 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P1
4
/CNTR
0
pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR
0
pin.
When the CNTR
0
active edge switch bit is
“
0
”
, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR
0
pin is
“
H
”
. The count is stopped while the
pin is
“
L
”
. Also, when the CNTR
0
active edge switch bit is
“
1
”
, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR
0
pin is
“
L
”
. The count
is stopped while the pin is
“
H
”
.
Timer X can stop counting by setting
“
1
”
to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to
“
1
”
.
Note on Timer X is described below;
I
Note on Timer X
CNTR
0
interrupt active edge selection
CNTR
0
interrupt active edge depends on the CNTR
0
active edge
switch bit.
When this bit is
“
0
”
, the CNTR
0
interrupt request bit is set to
“
1
”
at
the falling edge of CNTR
0
pin input signal. When this bit is
“
1
”
, the
CNTR
0
interrupt request bit is set to
“
1
”
at the rising edge of
CNTR
0
pin input signal.
G
Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to
“
1
”
.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows. The value of timer X latch is set to Timer X when
Timer X underflows.
When writing to Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, writing to
“
latch only
”
or
“
latch and prescaler (timer)
”
can
be selected by the setting value of the timer X write control bit.
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can be selected in one of 4 operating modes by setting
the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach
“
00
16
”
, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach
“
00
16
”
, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)
(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR
0
pin.
The output level of CNTR
0
pin can be selected by the CNTR
0
ac-
tive edge switch bit. When the CNTR
0
active edge switch bit is
“
0
”
,
the output of CNTR
0
pin is started at
“
H
”
level. When this bit is
“
1
”
,
the output is started at
“
L
”
level.
Also, the inverted waveform of pulse output from CNTR
0
pin can
be output from TX
OUT
pin by setting
“
1
”
to the P0
3
/TX
OUT
output
valid bit.
When using a timer in this mode, set the port P1
4
and P0
3
direc-
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P1
4
/CNTR
0
pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR
0
pin input signal can be selected from
rising or falling by the CNTR
0
active edge switch bit .
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