參數(shù)資料
型號: 7544
英文描述: 3.3V LDO POSITVE VOLTAGE REGULATOR 2% TOL.
中文描述: 7544Group數(shù)據(jù)表數(shù)據(jù)表503K/JUN.25.03
文件頁數(shù): 36/54頁
文件大小: 503K
代理商: 7544
Rev.1.02 2003.06.25 page 36 of 53
7544 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 44 Block diagram of internal clock generating circuit (for ceramic/quartz-crystal resonator)
Fig. 45 Block diagram of internal clock generating circuit (for RC oscillation)
S
R
Q
S
R
Q
1/2
R
S
Q
Rf
1/4
1/2
WIT
instruction
STP instruction
Timing
φ
(Internal clock)
STP instruction
Interrupt request
Reset
Interrupt disable flag l
High-speed mode
Middle-speed mode
Main clock division
ratio selection bit
Double-speed mode
Ring oscillator mode
Ring oscillator
RING
X
OUT
X
IN
1/8
Main clock division ratio selection bit
Middle-, high-, low-speed mode
Ring oscillator mode
RESET
Prescaler 1
Timer 1
S
R
Q
S
R
Q
1/2
R
S
Q
1/4
1/2
WIT
instruction
STP instruction
Timing
φ
(Internal clock)
STP instruction
Interrupt request
Reset
Interrupt disable flag l
High-speed mode
Middle-speed mode
Main clock division
ratio selection bit
Double-speed mode
Ring oscillator mode
Ring oscillator
RING
X
OUT
X
IN
Delay
1/8
Main clock division ratio selection bit
Middle-, high-, low-speed mode
Ring
oscillator
mode
RESET
Prescaler 1
Timer 1
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