參數(shù)資料
型號(hào): 7643
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述: 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù): 15/120頁
文件大?。?/td> 1369K
代理商: 7643
Rev.1.00 Jul 30, 2003 page 15 of 119
7643 Group
Table 6 List of I/O port function
Name
Port P0
Port P1
Port P2
Input/Output
Input/Output,
individual bits
I/O format
CMOS input level
CMOS 3-state output
Non-port function
Lower address
output
Higher address
output
Data bus I/O
Related SFRs
CPU mode register A
Port control register
Ref. No.
(1)
P0
0
/AB
0
P0
7
/AB
7
P1
0
/AB
8
P1
7
/AB
15
P2
0
/DB
0
P2
7
/DB
7
P6
0
–P6
7
P7
0
,
P7
1
/HOLD,
P7
2
,
P7
3
/HLDA,
P7
4
P8
0
/SRDY,
P8
1
/SCLK,
P8
2
/SRXD,
P8
3
/STXD,
P8
4
/UTXD,
P8
5
/URXD,
P8
6
/CTS,
P8
7
/RTS
Pin
(2)
CPU mode register A
Port control register
Port P2 pull-up control
register
CPU mode register A
CPU mode register B
Port control register
CPU mode register A
CPU mode register B
Port control register
Interrupt polarity select register
CPU mode register A
Port control register
Clock control register
Timer 123 mode register
Port control register
Control signal I/O
CMOS input level/VIHL
input level
CMOS 3-state output
Port P3
(1)
(3)
(4)
(5)
CMOS input level
CMOS 3-state output
P3
0
/RDY–
P3
7
/RD
P4
0
/EDMA,
Port P4
P4
1
/INT
0
,
P4
2
/INT
1
,
P4
3
,P4
4
Control signal I/O
External interrupt
P5
0
/X
CIN
,
P5
1
/T
OUT
/
X
COUT
CMOS input level
CMOS 3-state output
(6)
(7)
Timer 1, Timer 2
output pin
Sub-clock generat-
ing input pin
P5
2
–P5
7
Port P5
CMOS input level
CMOS 3-state output
(8)
CMOS input level/TTL
input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
CMOS input level
CMOS 3-state output
(9)
Port control register
Port control register
Port control register
CPU mode register B
UART control registers
Serial I/O control register 1
Serial I/O control register 2
Port control register
Port P6
Port P7
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
Control signal I/O
Serial I/O I/O pin
UART I/O pin
Port P8
Notes 1
: For details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable
sections.
2
: Make sure that the input level at each pin is either 0 V or V
CC
during execution of the STP instruction.
When an input level is at an intermediate potential, a rush current will flow from V
CC
to V
SS
through the input-stage gate.
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