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參數(shù)資料
| 型號： | 7643 |
| 英文描述： | IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE |
| 中文描述： | 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03 |
| 文件頁數(shù)： | 36/120頁 |
| 文件大?。?/td> | 1369K |
| 代理商： | 7643 |
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Rev.1.00 Jul 30, 2003 page 36 of 119
7643 Group
Fig. 29 DMACx (x = 0, 1) block diagram
DMAC
The 7643 group is equipped with 2 channels of DMAC (direct
memory access controller) which enable high speed data transfer
from a memory to a memory without use of the CPU.
The DMAC initiates the data transfer with an interrupt factor speci-
fied by the DMAC channel x (x = 0, 1) hardware transfer request
source bit (DxCEN), or with a software trigger.
The DxTMS [DMA Channel x (x = 0, 1) Transfer Mode Selection
Bit] selects one of two transfer modes; cycle steal mode or burst
transfer mode. In the cycle steal mode, the DMAC transfers one
byte of data for each request. In the burst transfer mode, the
DMAC transfers the number of bytes data specified by the transfer
count register for each request. The count register is a 16-bit
counter; the maximum number of data is 65,536 bytes per one re-
quest.
Figure 29 shows the DMA control block diagram and Figure 30
shows the structure of DMAC related registers.
[DMAC Index and Status Register] DMAIS
The DMAC Index and Status Register consists of various control
bits for the DMAC and its status flags.
The DMA Channel Index Bit (DCI) selects which channel ( 0 or 1)
will be accessed, since the mode registers, source registers, des-
tination registers and transfer count register of both DMAC
channels share the same SFR addresses, respectively.
[DMAC Channel x (x = 0, 1) Mode Registers 1, 2] DMAxM1,
DMAxM2
The 16 bits of DMAC Channel x Mode Registers 1 and 2 control
each operation of DMAC channels 0 and 1.
When the DMAC Channel x (x = 0, 1) Write Bit (DxDWC) is “0”,
data is simultaneously written into each latch and register of the
Source Registers, Destination Register, and Transfer Count Reg-
isters. When this bit is “1”, data is written only into their latches.
When data is read from each register, it must be read from the
higher bytes first, then the lower bytes. When writing data, write to
the lower bytes first, then the higher bytes.
Interrupt
:
UART receive, UART transmit,
Serial I/O, INT
0
Signal
:
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP1OUT FIFO data existing
Interrupt
:
INT
1
, Timer 1
Signal
:
EP (endpoint) 1 receive/transmit
EP (endpoint) 2 receive/transmit
EP1OUT FIFO data existing
Case of DMAC
channel 0
Case of DMAC
channel 1
DMAC channel X
Channel X timing
generator
Channel X transfer
source register
Channel X transfer
destination register
Channel X transfer count register
Interrupt
generator
DMACx
interrupt request
Address bus
DxCEN
DxCRR
DxHRS0
DxSRCE
DxRLD
DRLDD
DxDRCE
DxDRID
DxRLD
DRLDD
Interrupt disable flag (I flag)
Temporary register
Index status register
DxUF
DxDAUE
Mode 1
register
DxTMS
DTSC
Mode 2
register
Channel X transfer
source latch
15
Channel X transfer
destination latch
15
Channel X transfer count latch
DxDWC
DxDWC
DxDWC
Data
bus
Data
bus
DxUF
DxSFI
0
0
15
0
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