參數(shù)資料
型號: 7643
英文描述: IrDA. protocol handler plus endec for DCE Apps, -40C to +85C, 18-SOIC 300mil, TUBE
中文描述: 7643Group數(shù)據(jù)表數(shù)據(jù)表1369K/JUL.30.03
文件頁數(shù): 51/120頁
文件大?。?/td> 1369K
代理商: 7643
Rev.1.00 Jul 30, 2003 page 51 of 119
7643 Group
[USB Endpoint x (x = 1, 2) IN Control Register] IN_CSR
This register contains the control and status information of the re-
spective IN Endpoints 1, 2.
Set the IN_PKT_RDY bit to “1” after the data packet has been
written to the IN FIFO. This bit is cleared to “0” when the data
transfer is completed. In a bulk IN transfer, this bit is cleared when
an ACK signal is received from the host. If an ACK signal is not re-
ceived, this bit (and the TX_NOT_EMPTY bit) remains as “1”. This
same data packet is sent after the next IN token is received. The
FLUSH bit is for flushing the data in the IN FIFO.
Fig. 44 Structure of USB endpoint x (x = 1, 2) IN control register
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