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SE R IAL I/ O
7751 Group User’s Manual
7–6
7.2 Block description
7.2.2 UARTi transmit/receive control register 0
Figure 7.2.3 shows the structure of UARTi transmit/receive control register 0. For bits 0 and 1, refer to
“7.2.1 (1) Internal/External clock select bit.”
For bit 7, refer to
“7.2.2 transfer data format.”
Fig. 7.2.3 Structure of UARTi transmit/receive control register 0
(1)
____ ____
By clearing this bit to “0” in order to select the CTS function, pins P8
0
and P8
4
function as CTS input
pins, and the input signal of “L” level to these pins becomes one of the transmission conditions.
By setting this bit to “1” in order to select the RTS function, pins P8
0
and P8
4
become RTS output
pins. When the receive enable bit (bit 2 at addresses 35
16
, 3D
16
) is “0” (reception disabled), the RTS
output pin outputs “H” level.
The output level of this pin becomes “L” when the receive enable bit is set to “1.” It becomes “H”
when reception starts and it becomes “L” when reception is completed.
(2)
Transmit register empty flag (bit 3)
This flag is cleared to “0” when the UARTi transmit buffer register’s contents are transferred to the
UARTi transmit register. When transmission is completed and the UARTi transmit register becomes
empty, this flag is set to “1.”
CTS/RTS select bit
Bit
1
BRG count source select bits
Bit name
At reset
RW
Functions
b7
b6
b5
b4
b3
b2
b1
b0
0 0 : f
2
/ f
4
0 1 : f
16
/ f
32
1 0 : f
64
/ f
128
1 1 : f
512
/ f
1024
UART0 transmit/receive control register 0 (Address 34
16
)
UART1 transmit/receive control register 0 (Address 3C
16
)
b1 b0
0 : CTS function selected.
1 : RTS function selected.
Transmit register empty flag
0 : Data present in transmit register.
(During transmitting)
1 :
No data present in transmit register.
(Transmitting completed)
1
0
0
0
7
Transfer format select bit
(Used in clock synchronous
serial I/O mode)
(Note)
0 : LSB (Least Significant Bit) first
1 : MSB (Most Significant Bit) first
0
0
2
RW
RW
RO
3
RW
6 to 4
Nothing is assigned.
Undefined
–
RW
Note:
Fix bit 7 to “0” in the UART mode or when Serial I/O is ignored.