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7751 Group User’s Manual
ST OP MODE
10–4
10.2.1 Termination by interrupt request occurrence
When terminating Stop mode by interrupt request occurrence, instructions are executed after a certain time
measured by the watchdog timer has passed.
When an interrupt request occurs, the oscillator starts oscillating. Simultaneously, supply of , clock
φ
1
,
f
2
/f
4
to f
512
/f
1024
, Wf
32
/Wf
64
, and Wf
512
/Wf
1024
starts.
The watchdog timer starts counting owing to the oscillation start. The watchdog timer counts Wf
32
/Wf
64
.
When the watchdog timer’s MSB becomes “0,” supply of
φ
CPU
,
φ
BIU
starts. At the same time, the watchdog
timer’s count source returns to Wf
32
/Wf
64
or Wf
512
/Wf
1024
that is selected by the watchdog timer frequency
select bit (bit 0 at address 61
16
).
The interrupt request which occurs in
is accepted.
Table 10.2.2 lists the interrupts used to terminate Stop mode.
Table 10.2.2 Interrupts used to terminate Stop mode
Interrupt
____
i
interrupt (i = 0 to 2)
Timer Ai interrupt (i = 0 to 4)
Timer Bi interrupt (i = 0 to 2)
UARTi transmit interrupt (i = 0, 1)
UARTi receive interrupt (i = 0, 1)
Conditions for using each function to generate interrupt request
10.2 Operation description
Enabled in event counter mode
Enabled when selecting external clock
Notes 1:
Since the oscillator has stopped oscillating, each function does not work unless they are operated
under the above condition. Also, the A-D converter does not work.
2:
Since the oscillator has stopped oscillating, no interrupts other than those above can be used.
3:
Refer to
“Chapter 4. INTERRUPT”
and the description of each internal peripheral device for
details about each interrupt.
Before executing the
STP
instruction, enable interrupts used to terminate Stop mode.
In addition, the interrupt priority level of the interrupt used to terminate Stop mode must be higher than the
processor interrupt priority level (IPL) of the routine where the
STP
instruction is executed. When multiple
interrupts in Table 10.2.2 are enabled, Stop mode is terminated by the first interrupt request.
There is possibility that all interrupt requests occur after the oscillation starts in
and until supply of
and
(Note)
after the watchdog timer’s MSB becomes “0.”
For interrupts not to be accepted, set their interrupt priority levels to level 0 (interrupt disabled) before
executing the
STP
instruction.
CPU
BIU
starts in
. The interrupt requests which occur during this time are accepted in order of priority
Note :
The interrupt request which has the highest priority is accepted first.
φ
φ