- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1888 > 78P2351-IGTR/F (Maxim Integrated Products)LINE INTERFACE UNIT 100-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | 78P2351-IGTR/F |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 39/42頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | LINE INTERFACE UNIT 100-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | E4，OC-3，STM1-E |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP |
| 供應(yīng)商設(shè)備封裝： | 100-LQFP（16x16） |
| 包裝： | 帶卷 (TR) |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)當(dāng)前第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 6 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
Plesiochronous Tx Serial Mode
Figure 3 represents a common condition where a
serial transmit clock is not available and/or the data
is not source synchronous to the reference clock
provided to the 78P2351.
In this mode, the
78P2351 will recover a transmit clock from the serial
plesiochronous data and bypass the internal FIFO
and re-timing block. This mode is commonly used
for mezzanine cards, modules, and any application
where the reference clock can’t always be
synchronous to the transmit source clock/data.
TDK
78P2351
Framer/
Mapper
NRZ
140 / 155 MHz
Reference
Clock
SODP/N
SOCKP/N
SIDP/N
CKREFP
RXP/N
CMIP/N
XFMR
CMI
Coax
XO
Figure 3: Plesiochronous data only
(Tx CDR enabled, FIFO bypassed)
Synchronous Parallel Modes
In parallel modes, 4-bit CMOS data segments are
input to the chip with a 34.816MHz (E4
÷ 4) or
38.88MHz (STM1
÷ 4) synchronous clock. These
inputs are re-timed in a 4x8 clock decoupling FIFO
and then to a serializer for transmission. Because
the data is passed through the FIFO and re-timed
using a synthesized clock, the transmit nibble clock
and data must be source synchronous to the
provided reference clock.
For maximum compatibility with legacy ASICs, the
78P2351 can operate in both slave and master clock
modes as shown in Figures 4 and 5 respectively.
Note: A loop-timing mode is also available to
allow external remote loopbacks (i.e. line
loopback in framer). In this mode, the FIFO is
still enabled, but the transmit data will be re-
timed using the recovered receive clock.
HW Control Pins
SW Control Bits
Parallel
Mode
SDI_PAR
CKMODE
PAR
PMODE
Slave
High
Low
1
0
Slave +
*Loop-timing
High
Float
1
0
Master
High
1
*To enable loop-timing in software mode, set
SMOD[1:0]=11
4-bit CMOS TTL
TDK
78P2351
Framer/
Mapper
Reference
Clock
CKREFP/N
RXP/N
CMIP/N
XFMR
CMI
Coax
PO[3:0]D
POCK
PIxCK
PI[3:0]D
34/39 MHz
Figure 4: Slave Parallel Mode
4-bit CMOS TTL
TDK
78P2351
Framer/
Mapper
Reference
Clock
CKREFP/N
RXP/N
CMIP/N
XFMR
CMI
Coax
PO[3:0]D
POCK
PTOCK
PI[3:0]D
34/39 MHz
Figure 5: Master Parallel Mode
Transmit FIFO Description
Since the reference clock and transmit clock/data go
through different delay paths, it is inevitable that the
phase relationship between the two clocks can vary
in a bounded manner due to the fact that the
absolute delays in the two paths can vary over time.
The transmit FIFO allows long-term clock phase drift
between the Tx clock and system reference clock,
not exceeding +/- 25.6ns, to be handled without
transmit error.
If the clock wander exceeds the
specified limits, the FIFO will over or under flow, and
the FERR register signal will be asserted.
This
signal can be used to trigger an interrupt.
This
interrupt event is automatically cleared when a FIFO
Reset (FRST) pulse is applied, and the FIFO is re-
centered.
Notes:
1) External remote loopbacks (i.e. loopback
within
framer)
are
not
possible
in
synchronous
operation
(FIFO
enabled)
unless the data is re-justified to be
synchronous to the system reference clock
or the 78P2351 is configured for loop-timing
operation.
2) During IC power-up or transmit power-up,
the clocks going to the FIFO may not be
stable and cause the FIFO to overflow or
underflow. As such, the FIFO should be
manually reset using FRST anytime the
transmitter is powered-up.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 78P2351R-IMR/F | IC LIU NRZ-CMI CONV 155M 56-QFN |
| 78P2352-IELR/F | IC LIU SDH SONET 2CH 128-LQFP |
| 78Q2120C09-64CGTR/F | TXRX 10/100 BASE 3.3V 64-LQFP |
| 78Q2133/F | TXRX 10/100 MDIX 3.3V IND 32-QFN |
| 78Q8392LA03-28CHR/F | TXRX 10BASE 2/5 ETH COAX 28-PLCC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 78P2351R | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-DB | 功能描述:界面開發(fā)工具 78P2351R Demo Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| 78P2351R-IM | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
| 78P2351R-IM/F | 功能描述:接口 - 專用 Serial 155M NRZ to CMI Converter RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| 78P2351R-IMR | 制造商:TERIDIAN 制造商全稱:TERIDIAN 功能描述:Serial 155M NRZ to CMI Converter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。