2006 Teridian Semiconductor Corporation Rev." />
參數(shù)資料
型號: 78P2351-IGTR/F
廠商: Maxim Integrated Products
文件頁數(shù): 9/42頁
文件大小: 0K
描述: LINE INTERFACE UNIT 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1,000
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: E4,OC-3,STM1-E
電源電壓: 3.15 V ~ 3.45 V
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-LQFP(16x16)
包裝: 帶卷 (TR)
78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 17 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
PIN DESCRIPTION
LEGEND
TYPE
DESCRIPTION
TYPE
DESCRIPTION
A
Analog Pin
(Tie unused pins to ground)
PO
LVPECL-Compatible Differential Output
(Tie unused pins to supply or leave floating)
CIS
CMOS Schmitt Trigger Input
(Tie unused pins to ground)
CO
CMOS Digital Output
(Leave unused pins floating)
CI
CMOS Digital Input
(Tie unused pins to ground)
COZ
CMOS Tristate Digital Output
(Leave unused pins floating)
CIU
CMOS Digital Input w/ Pull-up
OD
Open-drain Digital Output
(Leave unused pins floating)
CID
CMOS Digital Input w/ Pull-down
S
Supply
CIT
3-State CMOS Digital Input
G
Ground
PI
LVPECL-Compatible Differential Input
(Tie unused pins to ground)
TRANSMITTER PINS
NAME
PIN
TYPE
DESCRIPTION
PI0D
PI1D
PI2D
PI3D
24
25
26
27
CI
Transmit (Parallel Mode) Data Input:
Four-bit CMOS parallel (nibble) inputs. Data is latched in on the rising edge
(default) of the transmit parallel clock and serialized with the MSB (PIx3D)
transmitted first.
PICK
23
CIS
Transmit (Parallel Mode) Clock Input:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock input that must be
source synchronous with the reference clock supplied at the CKREFP/N pins.
Used only in Slave Parallel Mode and Loop-timing Parallel Mode.
PTOCK
28
CO
Transmit (Parallel Mode) Clock Output:
A 34.816 MHz (E4) or 38.88 MHz (STM1) CMOS clock output that is
intended to latch in synchronous parallel data. Active during reset. Used only
in Master Parallel Mode (output disabled in all other transmit modes).
SIDP
SIDN
8
9
PI
Transmit (Serial Mode) Data Input:
Differential NRZ data input. See Transmitter Operation section for more info
on different clocking/timing modes.
SICKP
SICKN
5
6
PI
Transmit (Serial Mode) Clock Input:
A 155.52MHz synchronous differential input clock used to clock in the serial
NRZ data. By default, data is clocked in on the rising edge of SICKP.
CMIP
CMIN
93
94
A
Transmit (CMI Mode) Analog Data Output:
A CMI encoded data signal output conforming to the relevant ITU-T G.703
pulse templates when properly terminated and transformer coupled to 75
cable.
Outputs are tri-stated when transmitter is disabled. Active, but
undefined during reset.
CMI2P
CMI2N
79
78
A
Transmit Monitor Output:
Redundant CMI transmit driver enabled by RCSL control.
TXCKP
TXCKN
96
97
PO
Transmit (Serial Mode) Clock Output:
A 2x line rate LVPECL clock output used to clock out the transmit CMI data.
Used for diagnostics or far end re-timing. Active during reset.
ECLP
ECLN
99
100
PO
Transmit (Optical Mode) LVPECL Data Output:
Transmit data outputs used for interfacing with optical transceiver modules
when in Fiber (NRZ pass through) mode.
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