78P2351
Single Channel
OC-3/ STM1-E/ E4 LIU
Page: 8 of 42
2006 Teridian Semiconductor Corporation
Rev. 2.4
LOOPBACK MODES
In SW mode, LLBK and RLBK bits in the Signal
Control register are provided to activate the local
and remote analog loopback modes respectively.
In HW mode, the LPBK pin can be used to activate
local and remote analog loopback paths as shown in
the table below.
LPBK pin Loopback Mode
Low
Normal operation
Float
Remote (analog) Loopback:
Recovered receive clock and data
looped back directly to the transmit
driver. The CMI decoder and most of
transmit path is bypassed (including the
redundant Tx monitor output)
High
Local (analog) Loopback:
Transmit clock and data looped back to
receiver at the analog media interface.
RXP/N
SODP/N
SOCKP/N
PO[3:0]D
POCK
PTOCK
PI[3:0]D
PICK
SICKP/N
SIDP/N
ECLP/N
TXCKP/N
CMIP/N
CMI2P/N
Rx CDR
CMI
Decoder
FIFO
Tx CDR
Lock Detect
CMI
Encoder
Lock Detect
Adaptive
Eq.
LOS Detect
PMOD, SMOD[1:0], PAR
LLBK
RLBK,
RDSL
CMI
Figure 7: Local (Analog) Loopback
RXP/N
SODP/N
SOCKP/N
PO[3:0]D
POCK
PTOCK
PI[3:0]D
PICK
SICKP/N
SIDP/N
ECLP/N
TXCKP/N
CMIP/N
CMI2P/N
Rx CDR
CMI
Decoder
FIFO
Tx CDR
Lock Detect
CMI
Encoder
Lock Detect
Adaptive
Eq.
LOS Detect
PMOD, SMOD[1:0], PAR
LLBK
RLBK,
RDSL
CMI
Figure 8: Remote (Analog) Loopback
In SW mode only, a Full Remote (digital) Loopback
bit FLBK is also available in the Advanced Tx
Control register. This loopback exercises the entire
Rx and Tx paths of the 78P2351 including the Tx
clock recovery unit. As such, the user must enable
either Serial Plesiochronous or Serial Loop-timing
transmit modes to utilize the Full Remote (digital)
Loopback.
Rx CDR
CMI
Decoder
RXxP/N
SOxDP/N
SOxCKP/N
POx[3:0]D
POxCK
PTOxCK
PIx[3:0]D
PIxCK
SIxCKP/N
SIxDP/N
FIFO
Tx CDR
Lock Detect
EACH CHANNEL: Rx
CMI
Encoder
ECLxP/N
CMIxP/N
TXxCKP/N
Lock Detect
EACH CHANNEL: Tx
Adaptive
Eq.
LOS Detect
PMOD, SMOD[1:0], PAR
LLBK
RLBK
CMI
Figure 9: Remote (Digital) Loopback
INTERNAL POWER-ON RESET
Power-On Reset (POR) function is provided on chip.
Roughly 50
s after Vcc reaches 2.4V at power up,
a reset pulse is internally generated. This resets all
registers to their default values as well as all state
machines within the transceiver to known initial
values. The reset signal is also brought out to the
PORB pin.
The PORB pin is a special function
analog pin that allows for the following:
Override the internal POR signal by driving in
an external active low reset signal;
Use the internally generated POR signal to
trigger other resets;
Add external capacitor to slow down the
release of power-on reset (approximately 8
s
per nF added).
NOTE: Do not pull-up the PORB pin to Vcc or drive
this pin high during power-up. This will prevent the
internal reset generator from resetting the entire chip
and may result in errors.