參數(shù)資料
型號： 79RC32K438300BBI
廠商： Integrated Device Technology, Inc.
英文描述： IDTTM InterpriseTM Integrated Communications Processor
中文描述： IDTTM InterpriseTM集成通信處理器
文件頁數(shù)： 10/59頁
文件大小： 644K
代理商： 79RC32K438300BBI
10 of 59
May 25, 2004
IDT 79RC32438
GPIO[30]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: PCIMUINTN
Alternate function: PCI Messaging unit interrupt output.
GPIO[31]
I/O
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
SPI Interface
SCK
I/O
Serial Clock
. This signal is used as the serial clock output in SPI mode and in
PCI satellite mode with suspended CPU execution during PCI serial EEPROM
loading. This pin may be configured as a GPIO pin.
SDI
I/O
Serial Data Input
. This signal is used to shift in serial data in SPI mode and in
PCI satellite mode with suspended CPU execution during PCI serial EEPROM
loading. This pin may be configured as a GPIO pin.
SDO
I/O
Serial Data Output
. This signal is used shift out serial data in SPI mode and in
PCI satellite mode with suspended CPU execution during PCI serial EEPROM
loading. This pin may be configured as a GPIO pin.
I
2
C Bus Interface
SCL
I/O
I
2
C Clock.
I
2
C-bus clock.
SDA
I/O
I
2
C Data Bus.
I
2
C-bus data bus.
Ethernet Interfaces
MII0CL
I
Ethernet 0 MII Collision Detected.
This signal is asserted by the ethernet PHY
when a collision is detected.
MII0CRS
I
Ethernet 0 MII Carrier Sense.
This signal is asserted by the ethernet PHY
when either the transmit or receive medium is not idle.
MII0RXCLK
I
Ethernet 0 MII Receive Clock.
This clock is a continuous clock that provides a
timing reference for the reception of data.
MII0RXD[3:0]
I
Ethernet 0 MII Receive Data.
This nibble wide data bus contains the data
received by the ethernet PHY.
MII0RXDV
I
Ethernet 0 MII Receive Data Valid.
The assertion of this signal indicates that
valid receive data is in the MII receive data bus.
MII0RXER
I
Ethernet 0 MII Receive Error.
The assertion of this signal indicates that an
error was detected somewhere in the ethernet frame currently being sent in the
MII receive data bus.
MII0TXCLK
I
Ethernet 0 MII Transmit Clock.
This clock is a continuous clock that provides a
timing reference for the transfer of transmit data.
MII0TXD[3:0]
O
Ethernet 0 MII Transmit Data.
This nibble wide data bus contains the data to
be transmitted.
MII0TXENP
O
Ethernet 0 MII Transmit Enable.
The assertion of this signal indicates that data
is present on the MII for transmission.
MII0TXER
O
Ethernet 0 MII Transmit Coding Error.
When this signal is asserted together
with MIITXENP, the ethernet PHY will transmit symbols which are not valid data
or delimiters.
MII1CL
I
Ethernet 1 MII Collision Detected.
This signal is asserted by the ethernet PHY
when a collision is detected.
Signal
Type
Name/Description
Table 1 Pin Description (Part 7 of 9)
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