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參數(shù)資料
| 型號： | 79RC32K438300BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 3/59頁 |
| 文件大?。?/td> | 644K |
| 代理商： | 79RC32K438300BBI |
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May 25, 2004
IDT 79RC32438
card application, or as the primary PCI controller in the system. The PCI
interface can be operated synchronously or asynchronously to the other
I/O interfaces on the RC32438 device.
Ethernet Interface
The RC32438 has two Ethernet Channels supporting 10Mbps and
100Mbps speeds to provide a standard media independent interface
(MII) off-chip, allowing a wide range of external devices to be connected
efficiently.
UART Interface
The RC32438 contains two completely separate serial channels
(UARTs) that are compatible with the industry standard 16550 UART.
System Integrity Functions
The RC32438 contains a programmable watchdog timer that gener-
ates NMI when the counter expires and an address space monitor that
reports errors in response to accesses to undecoded address regions.
General Purpose I/O Controller
The RC32438 contains 32 general purpose input/output pins. Each
pin may be used as an active high or active low level interrupt or non-
maskable interrupt input, and each signal may be used as a bit input or
output port.
I
2
C Interface
The standard I2C interface allows the RC32438 to connect to a
number of standard external peripherals for a more complete system
solution. The RC32438 supports both master and slave operations.
Debug Support
The RC32438 supports the industry standard Rev. 2.6 EJTAG inter-
face.
Thermal Considerations
The RC32438 consumes less than 2.7 W
peak power. It is guaran-
teed in a ambient temperature range of 0
°
to +70
°
C for commercial
temperature devices and - 40
°
to +85
°
for industrial temperature
devices.
Revision History
November 7, 2002
: Initial publication. Preliminary Information.
November 15, 2002
: Added footnotes to Tables 5, 9, and 10.
December 12, 2002
: Added Clock Speed parameter to PLL and
Core supply in Table 16.
December 19, 2002
: Release version.
January 13, 2003
: Changed Thermal Considerations to read less
than 2.7W instead of 2.5W, added values to CLK parameter in Table 5,
and revised EJTAG description.
February 4, 2003
: Revised description for EJTAG/JTAG pins in
Table 1. Changed DDRDM[7:0] from input/output to output only in Tables
1 and 2 and Logic Diagram. Added new section, Voltage Sense Signal
Timing, as part of EJTAG description.
March 4, 2003
: In Table 2, removed “pull-up” from PCI pin category
and from GPIO [24] and GPIO[30-26]. In Table 20, changed max. values
for VccSI/O, VccCore, and VccPLL.
July 9, 2003
: In Table 7: changed values for DDRDATA, DDRDM,
and DDRADDR—WEN signals, and deleted old footnote #3 and
changed values in new footnote #3. In Table 8, changed Tdo values.
Changed Figure 7. Changed values in Table 18, Power Consumption.
Removed IPBus Monitor feature which included changes to Tables 1, 2,
21, 24, and 25. Deleted Table 13 which resulted in a re-ordering of
subsequent tables.
March 8, 2004
: Added 300MHz speed grade.
May 25, 2004
: In Table 9, signals MIIxRXCLK and MIIxTXCLK, the
Min and Max values for Thigh/Tlow_9c were changed to 140 and 260
respectively and the Min and Max values for Thigh/Tlow_9d were
changed to 14.0 and 26.0 respectively.
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