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參數(shù)資料
| 型號： | 79RC32K438300BBI |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IDTTM InterpriseTM Integrated Communications Processor |
| 中文描述： | IDTTM InterpriseTM集成通信處理器 |
| 文件頁數(shù)： | 15/59頁 |
| 文件大?。?/td> | 644K |
| 代理商： | 79RC32K438300BBI |
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May 25, 2004
IDT 79RC32438
Boot Configuration Vector
The boot configuration vector is read by the RC32438 during a cold reset. The vector defines essential RC32438 parameters that are required
once the cold reset completes.
The encoding of the boot configuration vector is described in Table 3, and the vector input is illustrated in Figure 4. The value of the boot configura-
tion vector read in by the RC32438 during a cold reset may be determined by reading the Boot Configuration Vector (BCV) Register.
Miscellaneous
CLK
I
LVTTL
STI
EXTCLK
O
LVTTL
High Drive
COLDRSTN
I
LVTTL
STI
RSTN
I/O
LVTTL
Low Drive / STI
pull-up
pull-up on board
1.
External pull-up required in most system applications. Some applications may require additional pull-ups not identified in this table.
2.
Schmidt Trigger Input (STI).
3.
The PCI pins have internal pull-ups but they are too weak to guarantee system validity. Therefore, board pull-ups are mandatory
where indicated. GPIO alternate function pins for PCI must also have board pull-ups.
4.
PCIMUINTN is an alternate function of GPIO[30]. When configured as an alternate function, this pin is tri-stated when not asserted
(i.e., it acts as an open collector output).
5.
Use a 2.2K pull-up resistor for I2C pins.
Signal
Name/Description
MDATA[3:0]
CPU Pipeline Clock Multiplier
. This field specifies the value by which the PLL multi-
plies the master clock input (CLK) to obtain the processor clock frequency (PCLK). For
master clock input frequency constraints, refer to Table 3.1 in the RC32438 User Man-
ual.
0x0 - PLL Bypass
0x1 - Multiply by 3
0x2 - Multiply by 4
0x3 - Multiply by 6
0x4 - Multiply by 8
0x5 - reserved
0x6 - reserved
0x7 - reserved
0x8 - reserved
0xD - reserved
0xE - reserved
0xF - reserved
MDATA[5:4]
External Clock Divider
. This field specifies the value by which the IPBus clock
(ICLK), which is always 1/2 PCLK, is divided in order to generate the external clock
output on the EXTCLK pin.
0x0 - Divide by 1
0x1 - Divide by 2
0x2 - Divide by 4
0x3 - reserved
MDATA[6]
Endian.
This bit specifies the endianness.
0x0 - little endian
0x1 - big endian
Table 3 Boot Configuration Encoding (Part 1 of 2)
Function
Pin Name
Type
Buffer
I/O Type
Internal
Resistor
Notes
1
Table 2 Pin Characteristics (Part 4 of 4)
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