參數(shù)資料
型號(hào)： 79RC32K438300BBI
廠商： Integrated Device Technology, Inc.
英文描述： IDTTM InterpriseTM Integrated Communications Processor
中文描述： IDTTM InterpriseTM集成通信處理器
文件頁(yè)數(shù)： 20/59頁(yè)
文件大?。?/td> 644K
代理商： 79RC32K438300BBI
20 of 59
May 25, 2004
IDT 79RC32438
AC Timing Characteristics
Values given below are based on systems running at recommended operating temperatures and supply voltages, shown in Tables 15 and 16.
Figure 4 Cold Reset AC Timing Waveform
Signal
Symbol
Reference
Edge
200MHz
233MHz
266MHz
300MHz
Unit
Conditions
Timing
Diagram
Reference
Min
Max
Min
Max
Min
Max
Min
Max
Reset
COLDRSTN
1
1.
The COLDRSTN minimum pulse width is the oscillator stabilization time (OSC) plus 0.5 ms with V
cc
stable.
2.
The values for this symbol were determined by calculation, not by testing.
3.
RSTN is a bidirectional signal. It is treated as an asynchronous input.
Tpw_6a
2
none
OSC +
0.5
—
OSC +
0.5
—
OSC +
0.5
—
OSC +
0.5
—
ms
Cold reset
See Figures 4
and 5.
Trise_6a
none
—
5.0
—
5.0
—
5.0
—
5.0
ns
Cold reset
RSTN
3
(input)
Tpw_6b
2
none
2(CLK)
—
2(CLK)
—
2(CLK)
—
2(CLK)
—
ns
Warm reset
RSTN
3
(output)
Tdo_6c
COLDRSTN
falling
—
15.0
—
15.0
—
15.0
—
15.0
ns
Cold reset
MDATA[15:0]
(boot vector)
Thld_6d
COLDRSTN
rising
3.0
—
3.0
—
3.0
—
3.0
—
ns
Cold reset
Tdz_6d
2
COLDRSTN
falling
—
30.0
—
30.0
—
30.0
—
30.0
ns
Cold reset
Tdz_6d
2
RSTN falling
—
5(CLK)
—
5(CLK)
—
5(CLK)
—
5(CLK)
ns
Warm reset
Tzd_6d
2
RSTN rising
2(CLK)
—
2(CLK)
—
2(CLK)
—
2(CLK)
—
ns
Warm reset
Table 6 Reset and System AC Timing Characteristics
BOOT VECT
CLK
COLDRSTN
RSTN
MDATA[15:0]
BDIRN
BOEN
Tpw_6a
1
2
3
4
5
6
FFFF_FFFF
1.
COLDRSTN asserted by external logic.
The RC32438 asserts RSTN, asserts BOEN low, drives BDIRN low, disables EXTCLK, and tri-states the data
bus and all output pins in response.
2.
External logic begins driving valid boot configuration vector on the data bus, and the RC32438 starts sampling it.
3.
External logic negates COLDRSTN and tri-states the boot configuration vector on MDATA[15:0]. The boot configuration vector must not be tri-stated
before COLDRSTN is negated. The RC32438 stops sampling the boot configuration vector.
4.
The RC32438 starts driving the data bus, MDATA[15:0], negates BOEN, drives BDIRN high, and starts driving EXTCLK.
5.
RSTN negated by the RC32438.
6.
CPU begins executing by taking MIPS reset exception, and the RC32438 starts sampling RSTN as a warm reset input.
<= 16 CLK
clock cycles>= 4096 CLK clock cyc>= 4096 CLK clock cycles
EXTCLK
Tdz_6d
Thld_6d
Trise_6a
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