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IDT EJTAG System
EJTAG Processor Core Extensions
79RC32438 User Reference Manual
20 - 20
November 4, 2002
Notes
The specific implementation determines which exceptions can occur. Exceptions that are blocked in
Debug Mode are simply ignored, not causing updates in any state.
Handling of the exceptions causing Debug Mode re-enter are described below.
Exceptions on Imprecise Errors
Exceptions on imprecise errors are possible in Debug Mode due to a bus error on an instruction fetch or
data access, cache error, or machine check.
The IEXI bit in the Debug register blocks imprecise error exceptions on entry or re-entry into Debug
Mode. They can be re-enabled by the debug exception handler once sufficient context has been saved to
allow a safe re-entry into Debug Mode and the debug handler.
Pending exceptions due to instruction fetch bus errors, data access bus errors, cache errors, and
machine checks are indicated and controlled by the IBusEP, DBusEP, CacheEP and MCheckP bit in the
Debug register.
The SYNC instruction, followed by appropriate spacing, must be executed in Debug Mode before the
IBusEP, DBusEP, CacheEP, and MCheckP bits are read in order to ensure that all pending causes for
imprecise errors are resolved and all bits are fully updated.
Those bits required to handle the possible imprecise errors in an implementation are implemented as R/
W, otherwise they are read only.
Debug Mode Exception Processing
All exceptions that are allowed in Debug Mode (except for reset and soft reset) have the same basic
processing flow:
The DEPC register is loaded with the PC at which execution will be restarted and the DBD bit is set
appropriately in the Debug register. The value loaded into the DEPC register is either the current
PC (if the instruction is not in the delay slot of a branch or jump) or the PC of the branch or jump if
the instruction is in the delay slot of a branch or jump).
The DSS, DBp, DDBL, DDBS, DIB, DINT, DDBLImpr, and DDBSImpr bits in the Debug register are
all cleared to differentiate from debug exceptions where at least one of the bits are set.
The DExcCode field in the Debug register is updated to indicate the type of exception that occurred.
Debug Breakpoint; execution of SDBBP instruc-
tion
Re-enter Debug Mode as for
execution of the BREAK instruc-
tion
Other execution-based exceptions
Re-enter Debug Mode
Debug Data Break Load/Store address match
only or Debug Data Break Store address+data
value match
Blocked
Watch on data access
Address error on data access
Re-enter Debug Mode
TLB Refill on data access
TLB Invalid on data access
TLB Modified on data access
Cache error on data access
Bus error on data access
Lowest
Debug Data Break on Load address+data match Blocked
Priority
Event in Debug Mode
Debug Mode Handling
Table 20.14 Priority of Non-Debug and Debug Exceptions (Part 2 of 2)