參數(shù)資料
型號(hào)： 82803AAMRH-R
英文描述： Controller Miscellaneous - Datasheet Reference
中文描述： 控制器雜項(xiàng)-數(shù)據(jù)表參考
文件頁(yè)數(shù)： 11/52頁(yè)
文件大小： 322K
代理商： 82803AAMRH-R
82803AA MRH-R
R
Datasheet
11
1.4.
Register Interface
The MRH-R has internal configuration and control registers. These registers are accessed through the
SCK, CMD and SIO CMOS signal interface (ExSCK, ExCMD, and ExSIO for the ‘Expansion’
Channel). The internal registers in the RDRAM devices are also accessed through the same CMOS signal
interface (CHA_SCK, CHA_CMD, and CHA_SIO for ‘Stick’ Channel A; CHB_SCK, CHA_CMD, and
CHB_SIO for ‘Stick’ Channel B).
In addition, the MRH-R also provides a System Management Bus (SMBus) interface to read the SPD
EEPROM on the RIMM module. The SMBus interface consists of two CMOS signals, SMBDATA and
SMBCLK.
1.5.
Terminology
RAMBUS*
RSL
Rambus* Signaling Level is the name of the signaling technology used
by Rambus*.
Rclk
Rclk refers to the RSL bus’ high speed clock in a generic fashion, often
in the context of clock counts in timing specs.
RAC
Rambus* ASIC Cell. It is the embedded cell designed by Rambus* that
interfaces with the Rambus* devices using RSL signaling.
RMC
Rambus* Memory Controller. This is the logic that directly interfaces to
the RAC.
RIMM
Rambus* Interface Memory Module.
Components
Intel
82840 MCH
The Memory Controller Hub component that contains the CPU
interface, Rambus* controller, and AGP interface. It communicates with
the ICH over a proprietary interconnect called Hub Interface.
Intel
82803AA MRH-R
The Memory Repeater Hub for RDRAM.
‘Expansion’ Channel
The RSL bus which connects the Memory Controller Hub to the
MRH-R.
‘Stick’ Channel
The pair of RSL busses which connects an MRH-R to its RDRAM
devices. An MRH-R can support a maximum of 2 ‘stick’ channels,
‘Stick’ Channel A and ‘Stick’ Channel B.
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