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參數(shù)資料
| 型號(hào)： | 82803AAMRH-R |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁數(shù)： | 27/52頁 |
| 文件大小： | 322K |
| 代理商： | 82803AAMRH-R |
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82803AA MRH-R
R
Datasheet
27
4.
Functional Description
4.1.
MRH-R and the Direct RDRAM Channel
4.1.1.
Operation Overview
The MRH-R acts as a Direct RDRAM channel expander by duplicating the signal activities on the
‘expansion’ channel to the specified ‘stick’ channel and vice versa. There is a time delay between the
signal activities happening on the ‘expansion’ bus and the same signal activities on the ‘stick’ channels.
This time delay must be constant under all operating conditions. The delay for RSL signals and delay for
CMOS signals are different.
The MRH-R has the logic capability to help the MCH to maximize channel efficiency. This includes
doing Refresh, Precharge After Refresh, Nap Exit, Power-down Exit, RAC Current Calibrate, RAC
Current Calibrate & Sample, and Temperature Calibrate of devices on a channel upon request from the
MCH.
The MRH-R contains registers for configuration and control. These registers are accessed through a three
signal CMOS interface. The MRH-R implements a similar three signal CMOS interface for each ‘stick’
channel to reset and initialize RDRAMs. The same interface is used for accessing the internal registers of
the RDRAM devices.
4.1.2.
Signal and Protocol Overview
The ‘Expansion’ Channel (Ex) consists of the set of signals used to transmit information to and from the
MRH-Rs and the protocol that defines the format and sequencing of this information. Both the signals
and protocol of the ‘expansion’ channel are a superset of the their counterparts on the Direct RDRAM
‘stick’ channels. This allows efficient use of the multitude of ‘stick’ channels supported. Access can be
pipelined with and across the Direct RDRAM channels, and sufficient control bandwidth is provided so
that channel service operations such as refresh can proceed in parallel with fully pipelined memory
accesses.
A Direct RDRAM Channel consists of two groups of high speed (RSL) control signals, a high speed
(RSL) data bus, and a group of low speed CMOS control signals. The control signal groups are referred
to as the Row Request Bus and the Column Request Bus. Each of these request busses has a request
packet format associated with it—Row Request Packet (RRQP) and Column Request Packet (CRQP).
Row and Column request packets can be pipelined to maximize data throughput to and from the memory.
To achieve full bandwidth operation on the ‘expansion’ channel, all control operations must be pipelined
with the memory request packets. Further, independent expansion control must be allocated for the Row
Request (RRq) and Column Request (CRq) packets on the ‘stick’ channels to maintain the variable RAS
to CAS timings. This requirement results in two extra signals on the ‘expansion’ channel—Row Control
Bus (EXP1), and Column Control Bus (EXP0).
Control packets on the ‘expansion’ channel are issued using EXP1 and EXP0 with the corresponding
Row Request and Column Request packets. They are used to select the MRH-R that supports the targeted
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