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| 型號： | 82845MP |
| 廠商： | INTEL CORP |
| 元件分類： | 外設(shè)及接口 |
| 英文描述： | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 中文描述： | MULTIFUNCTION PERIPHERAL, PBGA593 |
| 封裝： | 37.50 X 37.50 MM, FCBGA-593 |
| 文件頁數(shù)： | 24/157頁 |
| 文件大小： | 1407K |
| 代理商： | 82845MP |
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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
24
Datasheet
250687-002
R
2.3.
Hub Interface Signals
Table 6. Hub Interface Signal Descriptions
Signal Name
Type
Description
HI_[10:0]
I/O
CMOS
Hub Interface Signals:
Signals used for the hub interface.
HI_STB
I/O
CMOS
Hub Interface Strobe:
One of two differential strobe signals used to transmit or
receive packet data over hub interface.
HI_STB#
I/O
CMOS
Hub Interface Strobe Compliment:
One of two differential strobe signals used to
transmit or receive packet data over hub interface.
2.4.
AGP Interface Signals
2.4.1.
AGP Addressing Signals
Table 7. AGP Addressing Signal Descriptions
Signal Name
Type
Description
PIPE#
I
AGP
Pipelined Read:
This signal is asserted by the AGP master to indicate a full width
address is to be enqueued on by the target using the
AD
bus. One address is placed
in the AGP request queue on each rising clock edge while
PIPE#
is asserted. When
PIPE
# is deasserted no new requests are queued across the AD bus.
During SBA Operation:
This signal is
not used
if SBA (Side Band Addressing) is
selected.
During FRAME# Operation:
This signal is
not used
during AGP FRAME#
operation.
PIPE#
is a sustained tri-state signal from the AGP masters (graphics controller) and
is an MCH-M input.
SBA[7:0]
I
AGP
Side-band Address:
These signals are used by the AGP master (graphics
controller) to place addresses into the AGP request queue. The
SBA
bus and AD
bus operate independently. That is, transaction can proceed on the
SBA
bus and
the AD bus simultaneously.
During PIPE# Operation:
These signals are
not used
during PIPE# operation.
During FRAME# Operation:
These signal are
not used
during AGP FRAME#
operation.
Note:
When sideband addressing is disabled, these signals are isolated (no
external/internal pull-ups are required).
NOTE:
The above table contains two mechanisms, SBA and PIPE#, to queue requests by the AGP master. Note
that the master can only use one mechanism. The master may not switch methods without a full reset of
the system. When PIPE# is used to queue addresses, the master is not allowed to queue addresses
using the SBA bus. For example, during configuration time, if the master indicates that it can use either
mechanism, the configuration software will select which mechanism the master will use. Once this choice
has been made, the master must continue to use the mechanism selected until the master is reset (and
reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism, but rather a
static decision when the device is first being configured after reset.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 82845Mx | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 82845GE | 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 8284A | Clock Generator and Driver for 8066, 8088 Processors |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 82845MX | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845MZ | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M) |
| 82845PE | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH) |
| 8284611SM | 制造商:Thomas & Betts 功能描述: |
| 828461-2 | 制造商:TE Connectivity 功能描述:19P CPC STECK-GEH - Bulk |
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