參數(shù)資料
型號(hào)： 82845MP
廠商： INTEL CORP
元件分類： 外設(shè)及接口
英文描述： Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述： MULTIFUNCTION PERIPHERAL, PBGA593
封裝： 37.50 X 37.50 MM, FCBGA-593
文件頁數(shù)： 95/157頁
文件大?。?/td> 1407K
代理商： 82845MP
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
95
R
3.8.16.
SSTS1 – Secondary PCI-PCI Status Register – Device #1
Address Offset:
Default Value:
Access:
Size:
1E-1Fh
02A0h
Read Only, Read/Write Clear
16 bits
SSTS1 is a 16-bit status register that reports the occurrence of error conditions associated with secondary
side (i.e. AGP side) of the “virtual” PCI-PCI bridge embedded within MCH-M.
Bit
Descriptions
15
Detected Parity Error (DPE1):
This bit is set to a 1 to indicate MCH-M’s detection of a parity error in
the address or data phase of AGP bus transactions. Software sets DPE1 to 0 by writing a 1 to this bit.
14
Reserved
13
Received Master Abort Status (RMAS1):
When the MCH-M terminates a Host-to-AGP with an
unexpected master abort, this bit is set to 1. Software resets this bit to 0 by writing a 1 to it.
12
Received Target Abort Status (RTAS1):
When an MCH-M-initiated transaction on AGP is
terminated with a target abort, RTAS1 is set to 1. Software resets RTAS1 to 0 by writing a 1 to it.
11
Signaled Target Abort Status (STAS1):
STAS1 is hardwired to a 0, since the MCH-M does not
generate target abort on AGP.
10:9
DEVSEL# Timing (DEVT1):
This 2-bit field indicates the timing of the DEVSEL# signal when the
MCH-M responds as a target on AGP, and is hardwired to the value 01b (medium) to indicate the
time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.
8
Master Data Parity Error Detected (DPD1):
Hardwired to 0. MCH-M does not implement G_PERR#
signal.
7
Fast Back-to-Back Capable (FB2B1):
This bit is hardwired to 1, since MCH-M as a target supports
fast back-to-back transactions to different targets on the AGP interface.
6
Reserved
5
66 MHz Capable (CAP66):
This bit is hardwired to 1 to indicate that AGP bus is capable of 66-MHz
operation.
4:0
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82845MX 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845MZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
8284611SM 制造商:Thomas & Betts 功能描述:
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