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| 型號： | 844S012BKI-01LF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | OTHER CLOCK GENERATOR, QCC56 |
| 封裝： | 8 X 8 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VLLD-2, VFQFN-56 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 847K |
| 代理商： | 844S012BKI-01LF |
ICS844S012BKI-01 REVISION A APRIL 2, 2010
19
2010 Integrated Device Technology, Inc.
ICS844S012I-01 Data Sheet
CRYSTAL-TO-LVDS/LVCMOS FREQUENCY SYNTHESIZER
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
θ
JA * Pd_total + TA
Tj = Junction Temperature
θ
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
θ
JA must be used. Assuming a moderate air
flow of 1 meter per second and a multi-layer board, the appropriate value is 27.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 1.341W * 27.5°C/W = 121.9°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 7. Thermal Resistance θJA for 56 Lead VFQFN, Forced Convection
Meters per Second
01
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
31.4°C/W
27.5°C/W
24.6°C/W
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