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參數(shù)資料
| 型號(hào)： | 935086530518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PLASTIC, LCC-68 |
| 文件頁數(shù)： | 94/112頁 |
| 文件大?。?/td> | 693K |
| 代理商： | 935086530518 |
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1996 Jun 27
82
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xC592
Notes to the DC characteristics
1. Conditions for:
a) The digital operating current measurement: all output pins disconnected; XTAL1 is driven with tr =tf = 10 ns;
VIL =VSS + 0.5 V; VIH =VDD 0.5 V; EA = RST = Port 0 = P1.6 = P1.7 = EW = VDD;
STADC = VSS; CRX0 = 2.7 V; CRX1 = 2.3 V.
b) The analog operating current measurement: Port 5 = AVDD; CAN: register 6: = 00H;
load current reference voltage source 100
A.
2. Conditions for:
a) The digital Idle mode supply current measurement: all output pins disconnected;
XTAL1 is driven with tr =tf = 10 ns; VIL =VSS + 0.5 V; VIH =VDD 0.5 V; Port 0 = P1.6 = P1.7 = EW=VDD;
EA = RST = STADC = VSS; CRX0 = 2.7 V; CRX1 = 2.3 V.
b) The analog Idle mode current measurement: Port 5 = AVDD; CAN: register 6: = 00H;
load current reference voltage source 100
A.
3. Conditions for:
a) The digital Idle and Sleep mode supply current measurement: all output pins disconnected;
XTAL1 is driven with tr =tf = 10 ns; VIL =VSS + 0.5 V; VIH =VDD 0.5 V;
Port 0 = P1.6 = P1.7 = EW = CRX0 = VDD; EA = RST = STADC = CRX1 = VSS;
CAN: register 6: = 00H, register 7: = 12H, register 8: = 02H, register 0: = 20H, wait 15tCY,
register 1: = 10H, wait for bit Sleep = 1.
b) The analog Idle and Sleep mode current measurement: Port5=AVDD;
load current reference voltage source 100
A.
4. Window devices have to be covered. Conditions for:
a) The digital Power-down mode supply current measurement: all output pins and Port 5 disconnected;
Port 0 = P1.6 = P1.7 = EW = CRX0 = VDD;
EA = RST = STADC = CRX1 = XTAL1 = AVREF+ = AVREF = CVSS =VSS;
AVDD =VDD, but current into AVDD pin is not comprised in digital Power-down current.
b) The analog Power-down mode supply current measurement: Port 5 = AVDD.
5. Capacitive loads on Port 0 and Port 2 may degrade the LOW level output voltage of ALE, Port 1 and Port 3.
During a HIGH-to-LOW transition on the Port 0 and Port 2 pins and a capacitive load
>100 pF, the ALE LOW level
may exceed 0.8 V. In the case that it is necessary to connect ALE to a Schmitt trigger input respectively use an
address latch with a Schmitt trigger STROBE input.
CAN output driver (VDD =5V ± 5%)
VOLT
LOW level output voltage
(CTX0 and CTX1)
Io = 1.2 mA; note 15
0.1
V
Io =10mA
0.6
V
VOHT
High level output voltage
(CTX0 and CTX1)
Io = 1.2 mA; note 15
VDD 0.1
V
Io = 10 mA; note 16
VDD 0.6
V
Reference (AVDD =5V ± 5%)
VREFOUT
REF output voltage
0.1 mA < IL < 0.1 mA;
CL = 10 nF; note 15;
bit Reference Active = HIGH
1
2AVDD0.1 12AVDD+0.1 V
IREFIN
REF input current
1.5 V
< VREFIN < AVDD1.5 V;
bit Reference Active = LOW
±10
A
SYMBOL
PARAMETER
CONDITIONS
MIN.
MAX.
UNIT
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