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參數(shù)資料
| 型號： | 935167440551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 74/112頁 |
| 文件大?。?/td> | 707K |
| 代理商： | 935167440551 |
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1996 Jun 27
64
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
14 INTERRUPT SYSTEM
External events and the real-time-driven on-chip
peripherals require service by the CPU asynchronous to
the execution of any particular section of code. To tie the
asynchronous activities of these functions to normal
program execution a multiple-source, two-priority-level,
nested interrupt system is provided. Interrupt response
latency is from 2.25
sto7.5 s when using a 16 MHz
crystal. The latency time strongly depends on the
sequence of instructions executed directly after an
interrupt request. During a CAN-DMA transfer the interrupt
system is disabled (see Section 13.5.17). The P8xCE598
acknowledges interrupt requests from fifteen sources as
follows:
INT0 and INT1: externally via pins 43 and 44
respectively
Timer 0 and Timer 1: from the two internal counters
– If the capture function remains unused and the
Capture Register contents are ‘don't care’ then the
corresponding input pins ‘CTnI’, with ‘n = 0 ... 3’, may
be used as positive and/or negative edge triggered
external interrupts INT2 to INT5. But note that they
can not terminate the Idle mode because the Timer 2
is switched off then.
Timer T2, 8 separate interrupts:
– 4 capture interrupts
– 3 compare interrupts
– An overflow interrupt.
ADC end-of-conversion interrupt
CAN Controller interrupt
UART serial I/O port interrupt.
Each interrupt vectors to a separate location in Program
Memory for its service program. Each source can be
individually enabled or disabled by a corresponding bit in
the IEN0 or IEN1 register, moreover each interrupt may be
programmed to a HIGH or LOW priority level using a
corresponding bit in the IP0 or IP1 register. Also all
enabled sources can be globally disabled or enabled. Both
external interrupts can be programmed to be
level-activated or transition-activated, and an active LOW
level allows ‘wire-ORing’ of several interrupt sources to the
input pin.
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