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參數(shù)資料
| 型號： | 935167560557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 X 2.70 MM, PLASTIC, QFP-80 |
| 文件頁數(shù)： | 35/112頁 |
| 文件大?。?/td> | 707K |
| 代理商： | 935167560557 |
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1996 Jun 27
29
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
13.3
Interface between CPU and CAN
The internal interface between the P8xCE598's CPU and
on-chip CAN-controller is achieved via the following four
SFRs (see Fig.13):
CANADR, to point to a register of the CAN-controller
CANDAT, to read or write data
CANCON, to read interrupt flags and to write commands
CANSTA, to read status information and to write DMA
pointer.
Additionally, the DMA-logic allows a high-speed data
exchange between the CAN-controller and the CPU's
on-chip Main RAM. For more information, see
Section 13.5.15 “Handling of the CPU-CAN interface”.
13.4
Hardware blocks of the CAN-controller
The P8xCE598 CAN-controller contains all necessary
hardware for high performance serial network
communications (see Fig.14 and Table 29).
It controls the communication flow through the area
network using the CAN-protocol. The CAN-controller
meets the following requirements:
Short message length
Bus access priority, determined by the message
identifier
Powerful error handling capability
Configuration flexibility to allow area network expansion
Guaranteed latency time for urgent messages;
– The latency time defines the period between the
initiation (Transmission Request) and the start of the
transmission on the bus. The latency time strongly
depends on a large variety of bus-related conditions.
In the case of a message being transmitted on the
bus and one distortion, the latency time can be up to
149 bit times (worst case). For more information see
Chapter 22, “CAN application information”.
handbook, full pagewidth
CANADR
DBH
CANDAT
DAH
CANCON
D9H
CANSTA
D8H
ADDRESS
DATA
CAN
CONTROLLER
MAIN
RAM
CPU
DMA
LOGIC
internal
bus
4 special function
registers
MGA158
DMA bus
Fig.13 Interface between CPU and CAN-controller.
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