- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36334 > 935242210551 (NXP SEMICONDUCTORS) SPECIALTY CONSUMER CIRCUIT, PQFP160 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935242210551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁(yè)數(shù)： | 105/147頁(yè) |
| 文件大?。?/td> | 526K |
| 代理商： | 935242210551 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)當(dāng)前第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)
1998 Apr 09
60
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 52 Protection bits
BIT
NUMBER
FUNCTION
FIXED 1
F
V
H
P3
P2
P1
P0
711111111
600001101
500110011
401010101
301100110
201011010
100111100
001101001
7.8.5
SYNCHRONIZATION SIGNALS
Horizontal, vertical and frame synchronization signals are
either carried beside the data stream on the extra sync
pins of DD1 (one pair of sync pins per D1 channel) or are
encoded as SAV and EAV in the 8-bit wide video signal
stream. For the 16-bit wide YUV stream sync signals are
always available on separate pins. For D1 video inputs the
SAA7146A is programmed to determine where to recover
the synchronization information (from the dedicated sync
pins or from the encoded SAV and EAV codes in the data
stream).
For D1 video outputs, the SAA7146A can be programmed
to deliver synchronization information both in SAV and
EAV codes as well as on the dedicated sync pins.
Non-standard rastered video signals are supported by
sync signals at the dedicated sync pins as well as via SAV
and EAV codes. The number of clock cycles, pixels per
line and lines per field can be non-standard. These number
can range from 1 up to 4095.
The signal at the HS pin can perform the following
functions:
HS: input only, the rising edge is selected to act as
timing reference
HREF: input only, gated with CREF, the rising edge is
selected as timing reference
HGT: I/O, HIGH during active video
ACT input only: HIGH during active video, inactive
during horizontal and vertical blanking
HGT and ACT: envelope all active pixels (there is no
active pixel outside HGT or ACT), but may also include
clock cycles marked as not valid pixels by means of
PXQ.
The vertical sync signal can perform the following
functions:
VS: input only positive or negative, one edge is selected
as timing reference:
– If selected edge of VS and selected edge of HS are
in phase, then begin 1st (odd) field
– If selected edges of VS and HS are out of phase, then
begin 2nd (even) field.
V-DMSD: input only, falling (trailing) edge is timing
reference:
– If falling edge of V-DMSD is in high phase of HREF,
then begin 1st (odd) field
– If falling edge of V-DMSD is in low phase of HREF,
then begin 2nd (even) field.
VGT: I/O, HIGH during active video, (no holes for
horizontal blanking)
FS: input only, positive or negative, frame sync,
(odd/even), (313/312, 263/262 lines) HIGH in one field,
LOW in the other, changes on full line boundaries only.
7.8.6
FIELD DETECTION
The fields are detected simultaneously at both D1 sync
inputs. The results are available in two status registers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935242210557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935262922551 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935262922557 | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 935242220551 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 935242220557 | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 935245650125 | 制造商:NXP Semiconductors 功能描述:Inverter 1-Element CMOS 5-Pin TSSOP T/R |
| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
| 9-3525-012 | 制造商:KEYSTONE 功能描述:MODIFIED 3525,VERSION E |
| 935252-5 | 制造商:C-H 功能描述:935252-5 |
| 935257650112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY ICSUBS TO 935257650112 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。