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參數(shù)資料
| 型號： | 935242210551 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁數(shù)： | 90/147頁 |
| 文件大?。?/td> | 526K |
| 代理商： | 935242210551 |
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1998 Apr 09
47
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 39 Secondary status register
110
FIDA
8
R
Field ID Port A: via the FIDESA bits in the ‘Initial setting of the
Dual D1 Interface’ (see Table 66), selected edge(s) of this
signal will set the corresponding bit in the ISR when enabled.
FIDB
7
R
Field ID Port B: via the FIDESB bits in the ‘Initial setting of the
Dual D1 Interface’ (see Table 66), selected edge(s) of this
signal will set the corresponding bit in the ISR when enabled.
PIN3
6
R
GPIO Pin 3: this bit reects the state of the general purpose
pin 3. Via the GPIO register, selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
PIN2
5
R
GPIO Pin 2: this bit reects the state of the general purpose
pin 2. Via the GPIO register, selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
PIN1
4
R
GPIO Pin 1: this bit reects the state of the general purpose
pin 1. Via the GPIO register selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
PIN0
3
R
GPIO Pin 0: this bit reects the state of the general purpose
pin 0. Via the GPIO register selected edge(s) of this signal will
set the corresponding bit in the ISR when enabled.
ECS
2
R
Event Counter Status: this bit reects the status of the four
(SSR) event counter status bits EC5S, EC4S, EC2S and
EC1S.
EC3S
1
R
Event Counter 3 Status: this bit is set when event counter 3
exceeds its threshold.
EC0S
0
R
Event Counter 0 Status: this bit is set when event counter 0
exceeds its threshold.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
114
PRQ
31
R
PCI Request Pending: this bit is set while the PCI has asserted its
REQ# signal and has not received a GNT# yet
PMA
30
R
PCI master access: this bit is active as long as the SAA7146A acts as a
master on the PCI-bus
RPS_RE1
29
R
RPS Task 1 Register access Error: this bit is set when the LDREG,
STREG or MASKWRITE command tries to access a non-existing
register. This bit is reset by writing a logic 1 to the RPS_E1 bit in the ISR
or when a new RPS Task 1 is started.
RPS_PE1
28
R
RPS Task 1 Page Error: this bit is set when the RPS Task 1 tries to
write to an address outside the 4-kbyte page. This bit is reset by writing
a logic 1 to the RPS_E1 bit in the ISR or when a new RPS Task 1 is
started.
RPS_A1
27
R
RPS Task 1 Active: this bit is set whenever RPS Task 1 is executing
and not staying in a wait condition or uploading the working registers
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
RESET
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