1998 Apr 09
82
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 62 YUV4:2:2 format
Table 63 YUV4:1:1 format
The following formats are planar YUV formats and use the three video FIFOs and three video DMA Channels 1, 2 and 3.
The byte phase of the first sample each line is defined by the 2 LSBs of every DMA base.
YUV4:4:4; Uand V sampled with every Y sample
YUV4:2:2; Uand V sampled co-sided with first Y sample (of 2 samples in-line)
YUV4:2:0; MPEG U and V sampled at upper left sample of 4 sample in square (2 × 2)
YUV-9 video; U and V sampled at selected sample of 16 samples in-square (4 × 4)
YUV1; YUYV, YUYV...
YUV2; YYUU, YYVV...
7.11.1.3
8-bit formats
Y8G; Only Y or inverted Y
α8; 8-bit alpha information, to be master-read through FIFO 2 and merged into RGB-24 with alpha.
There are two pseudo CLUT formats, which derives its bits from RGB-24 or YUV-24 by truncation, or by error diffusion
dither. The byte phase of the first sample each field is defined by 2 LSBs of DMA base.
RGB-8 (3 : 3 : 2); Red has 3 bits, Green has 3 bits, Blue has 2 bits
YUV8 (4 : 2 : 2); Y has 4 bits, U has 2 bits, V has 2 bits. Y = 0 doesn’t exist, to handle 16-bit colour formats for pseudo
CLUT. After dithering, Ymin =1.
All 8-bit formats are packed formats, 4 samples go into one Dword. The byte phase of the first sample of each line is
defined by the 2 LSBs of the DMA base. All except
α8 use FIFO 1.
Table 64 8-bit formats
PACKING WITHIN 32-BIT Dword
BIT 31 TO BIT 24
BIT 23 TO BIT 16
BIT 15 TO BIT 8
BIT 7 TO BIT 0
Y1
V0
Y0
U0
BUS CYCLE
PACKING WITHIN 32-BIT Dword
BIT 31 TO BIT 24
BIT 23 TO BIT 16
BIT 15 TO BIT 8
BIT 7 TO BIT 0
1Y1
V0
Y0
U0
2Y3
V4
Y2
U4
3Y7
V6
Y5
Y4
PACKING WITHIN 32-BIT Dword
BIT 31 TO BIT 24
BIT 23 TO BIT 16
BIT 15 TO BIT 8
BIT 7 TO BIT 0
pixel3
pixel2
pixel1
pixel0