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| 型號(hào)： | 935242220557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 22/148頁(yè) |
| 文件大小： | 692K |
| 代理商： | 935242220557 |
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1998 Apr 09
118
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.5
AUDIO CONFIGURATION
The configuration parameters are selected using two configuration registers, ACON1 and ACON2.
The ACON1 register is locally buffered. The download from the shadow register into the working register is performed
when a DMA protection address is reached or immediately when both interfaces are not active (switched off, initial state).
Table 103 Audio Conguration Register 1 (ACON1)
Table 104 Audio Conguration Register 2 (ACON2)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F4
AUDIO_MODE [2:0]
31 to 29
RW
denes interface activation and combination
MAXLEVEL [6:0]
28 to 22
RW
denes the maximum allowed absolute value for the most
signicant byte of an audio sample
A1_SWAP
21
RW
denes if input (captured) data is stuffed in little-endian or
big-endian format for A1 (4 byte swap if set)
A2_SWAP
20
RW
denes if input (captured) data is stuffed in little-endian or
big-endian format for A2 (4 byte swap if set)
WS0_CTRL [1:0]
19 and 18
RW
function control for WS0 line
WS0_SYNC [1:0]
17 and 16
RW
pulse position and width control for WS0 line
WS1_CTRL [1:0]
15 and 14
RW
function control for WS1 line
WS1_SYNC [1:0]
13 and 12
RW
pulse position and width control for WS1 line
WS2_CTRL [1:0]
11 and 10
RW
function control for WS2 line
WS2_SYNC [1:0]
9 and 8
RW
pulse position and width control for WS2 line
WS3_CTRL [1:0]
7 and 6
RW
function control for WS3 line
WS3_SYNC [1:0]
5 and 4
RW
pulse position and width control for WS3 line
WS4_CTRL [1:0]
3 and 2
RW
function control for WS4 line
WS4_SYNC [1:0]
1 and 0
RW
pulse position and width control for WS4 line
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
F8
A1_CLKSRC [4:0]
31 to 27
RW
denes the bit clock source for A1
A2_CLKSRC [4:0]
26 to 22
RW
denes the bit clock source for A2
INVERT_BCLK1
21
RW
input or output BCLK1 with inverted polarity
INVERT_BCLK2
20
RW
input or output BCLK2 with inverted polarity
BCLK1_OEN
19
RW
output enable BCLK1 (active LOW)
BCLK2_OEN
18
RW
output enable BCLK2 (active LOW)
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