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參數(shù)資料
| 型號(hào)： | 935242220557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | PLASTIC, SOT-316, SQFP-208 |
| 文件頁(yè)數(shù)： | 26/148頁(yè) |
| 文件大?。?/td> | 692K |
| 代理商： | 935242220557 |
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1998 Apr 09
121
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.16.5.4
Bit clock control
Specific to each audio interface, A1 or A2, is the programming of bit clock source.
Table 109 CLK source denition
7.16.6
SWITCHING AUDIO STREAMS
There are different levels of switching data streams on and off:
DMA transfer enable; switching a DMA channel
AUDIO_MODE; switching the two audio interfaces
WSx_CTRL; switching a physical channel.
The AUDIO_MODE and WSx_CTRL programming is locally buffered and gets loaded when the corresponding DMA
protection address is reached. When both interfaces are off, changes are loaded immediately.
If an audio interface is switched on, it will start working at TSL pointer reset. Disabling a DMA channel clears the
corresponding FIFO and sets the DMA pointers to their base address: this is the initial state. It is recommended to enable
the output DMA channels before activating the interface, since the output FIFO has to be filled with valid output data.
It is the responsibility of the software to configure data structures, TSL sequences and protection address in such a way,
that they match each other.
AX_CLKSRC [4:0]
(HEX)
A1 BIT CLOCK
A2 BIT CLOCK
1F to 13
reserved
12
ACLK divided-by-384
11
ACLK divided-by-256
10
ACLK divided-by-192
0F
ACLK divided-by-128
0E
ACLK divided-by-96
0D
ACLK divided-by-64
0C
ACLK divided-by-48
0B
ACLK divided-by-32
0A
ACLK divided-by-24
09
ACLK divided-by-16
08
ACLK divided-by-12
07
ACLK divided-by-8
06
ACLK divided-by-6
05
ACLK divided-by-4
04
ACLK divided-by-3
03
ACLK divided-by-2
02
ACLK
01
BCLK2
BCLK1
00
BCLK1
BCLK2
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