1998 Apr 09
20
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 1
Conguration space registers
ADDRESS
(HEX)
NAME
BIT
TYPE
DESCRIPTION
00
Device ID
31 to 16
RO 7146H
SAA7146A
Vendor ID
15 to 0
RO 1131H
Philips
04
Status Register
31
detected parity error
29
received master abort
28
received target abort
26 and 25
RO 01
DEVSEL# timing medium
24
data parity error detected
23
RO 1
fast back-to-back capable
Command
Register
9
RW
fast back-to-back enable
6
RW
parity error response
2
RW
bus master enable
1
RW
memory space
08
Class Code
31 to 8
RO 048000H
other multimedia device
Revision ID
7 to 0
RO 01H
reading these 8 bits returns 01H
0C
Latency
15 to 8
RW
this register species, in units of PCI-bus clocks, the
value of the latency timer for this PCI-bus master
10
Base Address
Register
31 to 9
RW
this value must be added to the register offset to claim
access to the programming registers; the lower 8 bits
are forced to zero
8to0
RO
2C
Subsystem ID
31 to 16
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0000H
Subsystem
vendor ID
15 to 0
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0000H
3C
Max_Lat
31 to 24
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 26H
Min_Gnt
23 to 16
RO
this value will be loaded after a PCI reset from external
hardware using the I2C-bus; the default value is 0FH
Interrupt Pin
15 to 8
RO 01H
The interrupt pin register tells which interrupt pin the
device uses. This device uses interrupt pin INTA#.
When these bits are read they return 01H.
Interrupt Line
7 to 0
RW
the interrupt line register tells which input of the system
interrupt controller the device’s interrupt pin is
connected to