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| 型號： | 935260698557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP160 |
| 封裝： | PLASTIC, SOT-322, QFP-160 |
| 文件頁數(shù)： | 97/148頁 |
| 文件大?。?/td> | 692K |
| 代理商： | 935260698557 |
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1998 Apr 09
52
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
7.6
General Purpose Inputs/Outputs (GPIO)
7.6.1
GENERAL
The SAA7146A has four general purpose I/O pins. For example, they could be used to signal to other devices a
power-down mode or to map an internal status bit to it, e.g. to detect a sync lost from the VBLK pin of the SAA7110.
Table 42 GPIO registers
Table 43 GPIO control register
7.7
Event counter
The event counters in the SAA7146A provide the possibility of obtaining a statistical look at the different interrupt sources.
For this purpose six counters are implemented in two registers (EC1R and EC2R). Each register contains one 12-bit
counter and two 10-bit counters. To be flexible in the information collected in the counters it is possible to map each
status bit to any counter. This is done via the Event Counter Source Select Register (ECSSR). The four 10-bit counters
and the two 12-bit counters are able to select one of the 64 possible sources (see Table 47). In addition to the counting,
it is possible to generate interrupts via threshold values for the counters. These thresholds are kept in the two Event
Threshold Registers (ET1R and ET2R). If a counter exceeds its threshold, it is reset to zero and the corresponding status
bit is set.
Table 44 Event Counter set 1 Register (EC1R)
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
E0
GPIO3
31 to 24
RW
GPIO3 control register
GPIO2
23 to 16
RW
GPIO2 control register
GPIO1
15 to 8
RW
GPIO1 control register
GPIO0
7 to 0
RW
GPIO0 control register
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
DESCRIPTION
0
XXXX
input, no interrupt condition
0
1
XXXX
input, rising edge is interrupt condition
0
1
0
XXXX
input, falling edge is interrupt condition
0
1
XXXX
input, both edges are interrupt condition
0
1
X
0
XXXX
output, xed constant LOW
0
1
X
1
XXXX
output, xed constant HIGH
1
0
XXXXXX
reserved
1
SBA[5]
SBA[4]
SBA[3]
SBA[2]
SBA[1]
SBA[0] output, monitoring the selected status bits of
PSR or SSR; see Table 48
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
118
EC2 [9:0]
31 to 22
R
Event Counter Two: this is the second 10-bit counter
EC1 [9:0]
21 to 12
R
Event Counter One: this is the rst 10-bit counter
EC0 [1:0]
11 to 0
R
Event Counter Zero: this is the rst 12-bit counter
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