1998 Apr 09
31
Philips Semiconductors
Product specication
Multimedia bridge, high performance
Scaler and PCI circuit (SPCI)
SAA7146A
Table 6
Arbitration control registers
Table 7
Burst length denition
Table 8
Threshold denition
Note
1. The threshold is reached, if the FIFO contains at least this number of Dwords.
OFFSET
(HEX)
NAME
BIT
TYPE
DESCRIPTION
48
BurstDebi
28 to 26
RW
PCI burst length of the DEBI DMA channel; see Table 7
Burst3
20 to 18
RW
PCI burst length of video Channel 3; see Table 7
Thresh3
17 to 16
RW
threshold of FIFO 3; see Table 8
Burst2
12 to 10
RW
PCI burst length of video Channel 2; see Table 7
Thresh2
9 to 8
RW
threshold of FIFO 2; see Table 8
Burst1
4 to 2
RW
PCI burst length of video Channel 1; see Table 7
Thresh1
1 and 0
RW
threshold of FIFO 1; see Table 8
4C
BurstA1_in
28 to 26
RW
PCI burst length of audio input Channel 1; see Table 7
ThreshA1_in
25 to 24
RW
threshold of audio FIFO A1_in; see Table 8
BurstA1_out
20 to 18
RW
PCI burst length of audio output Channel 1; see Table 7
ThreshA1_out
17 and 16
RW
threshold of audio FIFO A1_out; see Table 8
BurstA2_in
12 to 10
RW
PCI burst length of audio input Channel 2; see Table 7
ThreshA2_in
9 and 8
RW
threshold of audio FIFO A2_in; see Table 8
BurstA2_out
4 to 2
RW
PCI burst length of audio output Channel 2; see Table 7
ThreshA2_out
1 and 0
RW
threshold of audio FIFO A2_out; see Table 8
VALUE
BURST LENGTH
000
1 Dword
001
2 Dwords
010
4 Dwords
011
8 Dwords
100
16 Dwords
101
32 Dwords
110
64 Dwords
111
128 Dwords
VALUE
WRITE MODE(1)
READ MODE(1)
VIDEO
AUDIO
VIDEO
AUDIO
00
4 Dwords of valid data
1 Dword of valid data
4 empty Dwords
1 empty Dword
01
8 Dwords of valid data
4 Dwords of valid data
8 empty Dwords
4 empty Dwords
10
16 Dwords of valid data
8 Dwords of valid data
16 empty Dwords
8 empty Dwords
11
32 Dwords of valid data
16 Dwords of valid data
32 empty Dwords
16 empty Dwords