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參數(shù)資料
| 型號： | 935261351112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉換 |
| 英文描述： | COLOR SIGNAL DECODER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SOT-232, SDIP-32 |
| 文件頁數(shù)： | 20/47頁 |
| 文件大?。?/td> | 390K |
| 代理商： | 935261351112 |
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1996 Jan 17
27
Philips Semiconductors
Preliminary specication
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
TDA9144
VA OUTPUT (PIN 11); ECL = 0
VOH
HIGH level output voltage
4.0
5
5.5
V
VOL
LOW level output voltage
0.2
0.4
V
Isink
sink current
2
mA
Isource
source current
2
mA
tW(VA)
VA pulse width
2.5/fH
50 Hz standard
160
s
3/fH
60 Hz standard
192
s
td
delay between start of vertical sync
pulse and positive edge of VA
note 5; see Fig.9
35
s
Zo
output impedance
ECL = 1
3
M
Sandcastle output (pin 10)
Vo
zero level output voltage
0
0.5
1
V
Isink
sink current
0.5
0.7
0.9
mA
HORIZONTAL AND VERTICAL BLANKING
Vbl
blanking voltage level
2.2
2.5
2.8
V
Isource
source current
0.5
0.7
0.9
mA
Iext
external current required to force the
output to the blanking level
1.0
3.0
mA
tW(H)
horizontal blanking pulse width
(69 LLC pulses)
10.0
s
td
delay between start of horizontal
blanking and start of clamping pulse
(44 LLC pulses)
6.4
s
CLAMPING PULSE
Vclamp
clamping voltage level
4.2
4.5
4.8
V
Isource
source current
0.5
0.7
0.9
mA
tW(clamp)
clamping pulse width
(25 LLC pulses)
3.6
s
td
delay between middle sync of input
and start of clamping pulse
note 4
3.0
3.2
3.4
s
YUV/RGB switches
Caution: the voltage on pin 3 must never exceed 5.5 V, if it does, the IC enters a test mode
RGB INPUTS (PINS 21, 20 AND 19 RESPECTIVELY); note 6
Vi(p-p)
input voltage (peak-to-peak value)
0.7
1
V
Zi
input impedance
3
M
Ci
input capacitance
5pF
UV INPUTS (PINS 3 AND 4 RESPECTIVELY); note 6
Vi(p-p)
U input voltage (peak-to-peak value)
1.33
1.90
V
Vi(p-p)
V input voltage (peak-to-peak value)
1.05
1.50
V
Zi
input impedance (both inputs)
3
M
Ci
input capacitance (both inputs)
5pF
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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