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參數(shù)資料
| 型號： | 935261351112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PDIP32 |
| 封裝： | 0.400 INCH, PLASTIC, SOT-232, SDIP-32 |
| 文件頁數(shù)： | 5/47頁 |
| 文件大小： | 390K |
| 代理商： | 935261351112 |
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1996 Jan 17
13
Philips Semiconductors
Preliminary specication
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
TDA9144
bit EMG = 1. I2C-bus bit EMG = 1 enables and EMG = 0
disables this sync gating in the horizontal PLL.
Vertical divider system
The vertical divider system has a fully integrated vertical
sync separator. The divider can accommodate both 50 Hz
and 60 Hz systems; it can either determine the field
frequency automatically or it can be forced to the desired
system via the I2C-bus. A block diagram of the vertical
divider system is illustrated in Fig.6.
The divider system operates at twice the horizontal
frequency. The line counter receives enable pulses at this
frequency, thereby counting two pulses per line. A state
diagram of the controller is shown in Fig.7. Because it is
symmetrical only the right-hand part will be described.
Depending on the previously found vertical frequency, the
controller will be in one of the COUNT states. When the
line counter has counted 488 pulses (i.e. 244 lines of the
video input signal), the controller will move to the next state
depending on the output of the norm counter. This can be
either NORM, NEAR_NORM or NO_NORM, depending
on the position of the vertical sync pulse in the previous
fields. When the controller is in the NORM state it
generates the vertical sync pulse (VSP) automatically and
then, when the line counter is at LC = 626, moves to the
WAIT state. In this condition it waits for the next pulse of
the double line frequency signal, and then moves to the
COUNT state of the current field frequency.
Fig.6 Block diagram of the vertical divider system.
handbook, halfpage
MGE043
NORM COUNTER
CONTROLLER
TIMING
GENERATOR
LINE COUNTER
When the controller returns to the COUNT state, the line
counter will be reset half a line after the start of the vertical
sync pulse of the video input signal. The NORM window
normally looks within one line width and a sudden half line
delay of the vertical sync pulse change can therefore be
neglected, but for PALplus conditions every half line shift
of the vertical sync pulse must be detected. In this case a
half line window is used.
When the controller is in the NEAR_NORM state it will
move to the COUNT state if it detects the vertical sync
pulse within the NEAR_NORM window (i.e.
622 < LC < 628). If no vertical sync pulse is detected the
controller will move back to the COUNT state when the line
counter reaches LC = 628. The line counter will then be
reset.
When the controller is in the NO_NORM state, it will move
to the COUNT state when it detects a vertical sync pulse
and reset the line counter. If a vertical sync pulse is not
detected before LC = 722 (if the
1 loop is locked, even in
forced mode) it will move to the COUNT state and reset the
line counter. If the
1 loop is not locked the controller will
return to the COUNT state when LC = 628.
The forced mode option keeps the controller in either the
left-hand side (60 Hz) or the right-hand side (50 Hz) of the
state diagram.
Figure 8 illustrates the state diagram of the norm counter
which is an up/down counter that increases its counter
value by 1 if it finds a vertical sync pulse within the selected
window. If not it decreases the counter value by 1 (or 2,
see Fig.8). In the NEAR_NORM and NORM states the first
correct vertical sync pulse after one or more incorrect
vertical sync pulses is processed as an incorrect pulse.
This procedure prevents the system from staying in the
NEAR_NORM or NORM state if the vertical sync pulse is
correct in the first field and incorrect in the second field.
In case of no sync lock (SLN = 1) the norm counter is reset
to NO_NORM (wide search window), for fast vertical
catching when switching between video sources. Fast
switching between different channels however can still
result in a continuous horizontal sync lock situation, when
the channel is changed before the norm counter has
reached the NORM state. To provide faster vertical
catching in this case, measures have been taken to
prevent the norm counter to count down to zero before
reaching the NO_NORM state (see left-hand of Fig.8). Bus
bit FWW (forced wide window) enables the norm counter
to stay in the NO_NORM state if desired. The
norm/no_norm status is read out by bus bit NRM.
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