參數(shù)資料
型號(hào)： 935261351112
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PDIP32
封裝： 0.400 INCH, PLASTIC, SOT-232, SDIP-32
文件頁(yè)數(shù)： 24/47頁(yè)
文件大?。?/td> 390K
代理商： 935261351112
1996 Jan 17
30
Philips Semiconductors
Preliminary specication
I2C-bus controlled, alignment-free PAL/NTSC/SECAM
decoder/sync processor with PALplus helper demodulator
TDA9144
Notes to the characteristics
1. All frequency variations are referred to 3.58 MHz or 4.43 MHz carrier frequency. All oscillator specifications are
measured with the Philips crystal series 9920 520 0047x and 9920 520 0048x. The oscillator circuit is insensitive to
the spurious responses of the crystal. The typical crystal parameters for the crystals mentioned above are:
a) Load resonance frequency f0 = 4.433619 MHz or 3.579545 MHz (CL = 20 pF).
b) Motional capacitance CM = 20.6 fF (4.43 MHz crystal) or 14.7 fF (3.58 MHz crystal).
c) Parallel capacitance C0 = 5 pF for both crystals.
d) The minimum detuning range can only be specified if both the IC and the crystal tolerances are known and the
general specifications given for the subcarrier regeneration are therefore valid for the specified crystal series. In
the figure tolerances of the crystal with respect to nominal frequency, motional capacitance and ageing have been
taken into account and have been counted for by Gaussian addition.
Whenever different typical crystal parameters are used, the following equation might be helpful for calculating the
impact on the detuning capabilities:
e) Detuning range proportional to:
f) The resulting detuning range should be corrected for temperature shift and supply deviation of both the IC and
the crystal. For the above mentioned crystals, the actual load capacitance in the application should be CL =18pF
to account for parasitic capacitance on and off chip. For 3-norm applications with two crystals connected to one
pin, the maximum load capacitance of the crystal pin should not exceed 12 pF.
2. YD3 and YD2 are equal significant bits, both representing a 160 ns delay step. YD1 represents 80 ns and YD0
represents a 40 ns delay step.
3. The Hue control is active for NTSC on the
(RY) and (BY) signals and for PALplus only on the demodulated
helper signal.
4. This delay is partially caused by the low-pass filter at the sync separator input.
5. The delay between the positive edge of VA and the first negative edge of HA (or positive edge of CLP) after VA is
34.5
s for field 1 and 2.5 s for field 2 (17 LLC pulses with or without
respectively). Especially for PALplus
signals the regenerated VA pulses must have a fixed and known phase relation to the undisturbed V pulses of the
incoming video signal. This relation must remain correct as long as the vertical divider is in norm mode (indirect sync
mode), so the coincidence window used here must be a half line compared to the one line coincidence window used
outside PALplus. With a well defined phase relation of the regenerated VA pulses to the regenerated HA pulses a
correct field identification (odd/even) and all the required timing signals referring to a certain line in each frame can
be generated externally in the PALplus decoder environment.
6. The output signals of the demodulator are called
(RY) and (BY) in this specification. The colour difference input
and output signals of the YUV switch are called UV signals. However, these signals do not have the amplitude
correction factor of real UV signals. They are called UV signals and not
(RY) and (BY) to prevent confusion
between the colour difference signals of the demodulator and the colour difference signals of the YUV switch.
7. The maximum external clamping pulse width is the minimum available blanking level time of the supplied RGB
signals.
C
M
1
C
O
C
L
--------
+
2
---------------------------
1
2f
H
×
--------------
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