- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄36460 > 9412AVK (MICRONAS SEMICONDUCTOR HOLDING AG) SPECIALTY CONSUMER CIRCUIT, PQFP80 PDF資料下載
參數(shù)資料
| 型號： | 9412AVK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 |
| 文件頁數(shù)： | 53/126頁 |
| 文件大?。?/td> | 1673K |
| 代理商： | 9412AVK |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁當(dāng)前第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁
DATA SHEET
32
Aug. 16, 2004; 6251-552-1DS
Micronas
2.6.1. Line-locked Clock Generator
The clock generation system derives all clocks from
one 20.25 MHz crystal oscillator clock source. An
internal PLL multiplies this oscillator frequency by 32,
generating a clock of 648 MHz which is used as refer-
ence for all clocks needed.
Line-locked horizontal sync pulses are generated by a
digital phase locked loop. The time constant can be
adjusted between fast and slow behavior (KPL, KIL) to
accommodate different backend ICs. The PLL control
can be frozen up to 15 lines before V-sync (FION) for a
duration up to 15 lines (FILE). This may be used to
reduce disturbances by h-phase errors which are pro-
duced by VCR’s. The output frequency for the 100/120
Hz version dependent on IICINCR is
A freerunning frequency is also generated which may
be selected alternatively. The freerunning frequency
for the 100/120 Hz version dependent on FRINC is
Normally, IICINCR and FRINC are equal or nearly the
same. The value is internally divided by two for the 50/
60 Hz versions.
The number of pixels generated by the PLL is given by
PPLIP. For line-locked clock generation the following
equation must be fulfilled:
Fig. 2–42: Line-locked Clock Ceneration
Fig. 2–43: Allowed Operation Area for Clock Generation
f
displayll
IICINCR 103Hz
=
f
displayfr
FRINC 103Hz
=
PPLIP
2 PPLOP
=
M
U
X
648MHz
ADC
phase
detector
PLL
20.25 MHz
xtal
oscillator
sync-
separation
loop
filter
LL-DTO
frequency
divider
analog
CVBS
inter-
polation
IICINCR
CLKF40
CLKF20
CLKB27
CLKB36
CLKB72
FR-DTO
frequency
divider
frequency
divider
FRINC
line-locked
locked or
freerunning
selection
nominal 100Hz
operation (analog out)
nominal 50Hz
operation (analog out)
13.5 / 18 27 / 36 MHz
nominal 50Hz
operation (digital out)
nominal 100Hz
operation (digital out)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9402AVK | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 94136-608T | 72 CONTACT(S), FEMALE, 40 DEGREE SINGLE PART CARD EDGE CONN, SOLDER, SOCKET |
| 94136-608 | 72 CONTACT(S), FEMALE, 40 DEGREE SINGLE PART CARD EDGE CONN, SOLDER, SOCKET |
| 94136-613K | 72 CONTACT(S), FEMALE, 40 DEGREE SINGLE PART CARD EDGE CONN, SOLDER, SOCKET |
| 94136-803K | 72 CONTACT(S), FEMALE, 40 DEGREE SINGLE PART CARD EDGE CONN, SOLDER, SOCKET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9412B1129429 | 功能描述:環(huán)形MIL規(guī)格工具、五金與附件 RoHS:否 制造商:Amphenol Industrial MIL 類型:MIL-DTL-5015 系列:97 產(chǎn)品類型:Dummy Receptacles 用于:97 Series Plugs |
| 9412-CHR-500 | 制造商:Belden Inc 功能描述:Computer Cable 4Conductors 24AWG 152.4m 4.67mm Tinned Copper Chrome 300VAC 1.75A Reel |
| 941-2MM | 功能描述:支架與墊片 Plastic Spcr 2mm Nylon White RoHS:否 制造商:Schurter 類型:Transipillar Spacers 長度:16 m 螺紋大小:M4 外徑:10 mm 材料:Nylon with Steel 電鍍:Zinc |
| 9412SMA | 制造商:Finder 功能描述:SOCKET & CLIP PCB DPCO RELAY |
| 9413 | 功能描述:螺絲和緊固件 1 1/4" 6-32 STEEL BD RoHS:否 制造商:Unspecified 產(chǎn)品: 類型:Washer 螺紋大小: 長度: 材料:Steel 電鍍:Nickel 螺絲頭: 螺絲類型: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。