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參數(shù)資料
| 型號(hào)： | 9412AVK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 |
| 文件頁數(shù)： | 56/126頁 |
| 文件大?。?/td> | 1673K |
| 代理商： | 9412AVK |
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DATA SHEET
Micronas
Aug. 16, 2004; 6251-552-1DS
35
The I2C parameter V20STAT, V40STAT and V36BSTAT
reflect the state of the register values.
If these bits are read as ‘1’, then the store command
was sent, but the data is not made available yet.
If these bits are ‘0’ then the data was made valid and a
new write or read cycle can start.
The bits V20STAT, V40STAT and V36BSTAT may be
checked before writing or reading new data, otherwise
data can be lost by overwriting. No V36FSTAT register
exist. To make the register values available to the four
I2C bus interface immediately after sending, the I2C
bus master has to write a ‘don’t care’ byte to the sub-
address FEh (store command).
For the read process, the I2C bus master must not
send a store command. In order to have a defined time
step for the I2C bus interface blocks in the different
domains, where the data will be available from the dif-
ferent blocks, the data is made valid with the same V-
Sync related signals mentioned above for the write
process.
The VSP 94x2A distinguishes between two different
types of read-registers. The behavior of the “normal”
read registers does not differ from the behavior of the
write registers. Only the direction of the data flow is
opposite.
The “rs typ” read registers behave differently. They can
be only set (means value 1) by the internal blocks
using the rising edge of a corresponding signal. After
reading by the I2C bus master, the registers will be
automatically reset (means value 0) by the I2C bus ker-
nel/interface. For example the register NMSTATUS
belongs to the “rs typ” read registers. NMSTATUS sig-
nalizes a new value for NOISEME. So if NMSTATUS is
read as ‘0’ the current noise measurement has not
been updated. If the NMSTATUS is read as ‘1’ a new
noise measurement value can be read. All other “rs
typ” read registers work in the same way. The “rs typ”
read registers will be marked in the overview with the
short cut “rstyp” or will have the additional hint “Note:
reset automatically when read/write” in the detailed I2C
bus command description.
By default all registers are made valid by the internal V-
Sync related signals and, in addition, a store command
has to be sent for write registers. The registers, which
should also be made available immediately as for writ-
ing and reading, are marked with the short cut NTO
(No take over mechanism).
Registers which need a hand-shake mechanism
between the I2C bus interface and the different blocks
are marked with the shortcut HS (Hand shake mecha-
nism). This means that all bits of the registers are used
when the last register is written. After PPLIP9-2 is writ-
ten, PPLIP1-0 must be written to allow these bits to
have effect.
The registers for the write parameter STOPMODE are
directly connected to the read registers of the parame-
ter SMMIRROR. So it is possible to check the I2C bus
protocol by writing and reading to the register STOP-
MODE and SMMIRROR, respectively.
The transmitted data is internally stored in registers.
Writing to or reading from a non-existant register is
permitted and does not generate a fault by the IC.
After switching on the IC, all bits of the VSP 94x2A are
set to defined states, (refer to Table 3–6). POR is set
after reset to pin 24. It stays ‘1’, until it is cancled via
software PORCNCL. This can be used to decide dur-
ing TV operation, whether to program all registers (e.g.
after power failure reset) or only altered ones (normal
TV operation).
Table 3–5: I2C bus clock domains
Domain
Description
Clock
CP
CP-CD
CVBS frontend
CLKF20
CP-PP
LL-PLL
CLKF20
CP-I2C
I2C read
CLKF20
FP
FP-PRE
Prescaler
CLKF40
FP-MC
Memory-controller
CLKF40
FP-RGB
RGB Frontend
CLKF40
FP-TNR
Temporal noise
reduction
CLKF40
FP-I2C
I2C read
CLKF40
PP
LL-PLL
CLKF36
PP-I2C
I2C read
CLKF36
BP
BP-DP
Display processing
CLKB36
BP-PM
Pixel-Mixer
CLKB36
BP-ODC
Output data control
CLKB36
BP-ODC/MC
Output data control/
memory-controller
CLKB36
BP-POS
Postscaler
CLKB36
BP-DAC
DAC processing
CLKB72
BP-I2C
I2C read
CLKB36
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